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Welcome to the 80286 80287 Microprocessor MCQs Page

Dive deep into the fascinating world of 80286 80287 Microprocessor with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of 80286 80287 Microprocessor, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of 80286 80287 Microprocessor, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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80286 80287 Microprocessor MCQs | Page 15 of 19

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Q141.
A valid HOLD request is ascertained only after the completion of

a.

34 clockcycles

b.

24 clockcycles and 80286 is SET

c.

34 clockcycles and 80286 is SET

d.

34 clockcycles and 80286 is RESET

Discuss
Answer: (d).34 clockcycles and 80286 is RESET
Q142.
The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of

a.

first INTA (active low) pulse from 80286

b.

second INTA (active low) pulse from 80286

c.

third INTA (active low) pulse from 80286

d.

none of the mentioned

Discuss
Answer: (a).first INTA (active low) pulse from 80286
Q143.
The slave (which is selected) sends the vector on data bus after the

a.

first INTA (active low) pulse from 80286

b.

second INTA (active low) pulse from 80286

c.

third INTA (active low) pulse from 80286

d.

none of the mentioned

Discuss
Answer: (b).second INTA (active low) pulse from 80286
Q144.
The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

a.

DEN

b.

DT/R (active low)

c.

MCE

d.

MB

Discuss
Answer: (c).MCE
Q145.
The LOCK (active low) signal is activated during

a.

Ti of first INTA cycle

b.

Ts of first INTA cycle

c.

Th of second INTA cycle

d.

Ts of second INTA cycle

Discuss
Answer: (b).Ts of first INTA cycle
Q146.
The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is

a.

1

b.

2

c.

3

d.

4

Discuss
Answer: (c).3
Q147.
In which of these modes, the immediate operand is included in the instruction itself?

a.

register operand mode

b.

immediate operand mode

c.

register and immediate operand mode

d.

none of the mentioned

Discuss
Answer: (b).immediate operand mode
Q148.
In register address mode, the operand is stored in

a.

8-bit general purpose register

b.

16-bit general purpose register

c.

si or di

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q149.
In which of the following addressing mode, the offset is obtained by adding displacement and contents of one of the base registers?

a.

direct mode

b.

register mode

c.

based mode

d.

indexed mode

Discuss
Answer: (c).based mode
Q150.
In which of the following addressing mode, the offset is obtained by adding displacement, with the contents of SI?

a.

direct mode

b.

register mode

c.

based mode

d.

indexed mode

Discuss
Answer: (d).indexed mode
Page 15 of 19

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