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Welcome to the 80286 80287 Microprocessor MCQs Page

Dive deep into the fascinating world of 80286 80287 Microprocessor with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of 80286 80287 Microprocessor, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of 80286 80287 Microprocessor, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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80286 80287 Microprocessor MCQs | Page 14 of 19

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Q131.
The number of bus controllers that are used for interfacing of memory and I/O devices is

a.

1

b.

2

c.

3

d.

none of the mentioned

Discuss
Answer: (b).2
Q132.
If the 80286 need to use system bus, then the signal that is to be active is

a.

SRDY

b.

SRDYEN

c.

ARDYEN

d.

ARDY

Discuss
Answer: (c).ARDYEN
Q133.
If MBYTES input is high, then the pin serves as

a.

AEN

b.

CEN

c.

AEN and CEN

d.

None of the mentioned

Discuss
Answer: (a).AEN
Q134.
Latches are used in 80286 to

a.

demultiplex the address and data lines

b.

latch the address signals

c.

decode the select signals

d.

latch the address and decode the select signals

Discuss
Answer: (d).latch the address and decode the select signals
Q135.
The I/O port addresses, that are not used, while designing practical systems around 80286 are

a.

0000H to 00FFH

b.

00FFH to FFFFH

c.

00F8H to 00FFH

d.

0000H to FFFFH

Discuss
Answer: (c).00F8H to 00FFH
Q136.
Which of the following is the highest priority usage among them?

a.

second transfer cycle of a processor extension data transfer

b.

third transfer cycle of a processor extension data transfer

c.

hold request

d.

second byte transfer of 2-byte transfer at an odd address

Discuss
Answer: (d).second byte transfer of 2-byte transfer at an odd address
Q137.
The highest priority usage than any other usage is

a.

transfer with LOCK (active low) signal

b.

hold request

c.

processor extension data transfer

d.

data transfer performed by EU (execution unit)

Discuss
Answer: (a).transfer with LOCK (active low) signal
Q138.
The lowest priority usage among the following is

a.

hold request

b.

processor extension data transfer

c.

prefetch operation to fetch and arrange next instruction bytes in queue

d.

data transfer performed by EU for instruction execution

Discuss
Answer: (c).prefetch operation to fetch and arrange next instruction bytes in queue
Q139.
As a response to the valid bus hold request, the bus is pushed into

a.

TH (hold) state

b.

Ts (status) state

c.

Tc (command) state

d.

Ti (idle) state

Discuss
Answer: (a).TH (hold) state
Q140.
The bus arbiter relinquishes

a.

Address

b.

M/IO (active low)

c.

COD/INTA (active low)

d.

All of the mentioned

Discuss
Answer: (d).All of the mentioned
Page 14 of 19

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