Q. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of

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Q. The slave (which is selected) sends the vector on data bus after the

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Q. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

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Q. The LOCK (active low) signal is activated during

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Q. The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is

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Q. In which of these modes, the immediate operand is included in the instruction itself?

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Q. In register address mode, the operand is stored in

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Q. In which of the following addressing mode, the offset is obtained by adding displacement and contents of one of the base registers?

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Q. In which of the following addressing mode, the offset is obtained by adding displacement, with the contents of SI?

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Q. The address of a location of the operand is calculated by adding the contents of any of the base registers, with the contents of any of index registers in

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Q. Which of the following is not a data type of 80286?

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Q. The representation of 8-bit or 16-bit signed binary operands using 2’s complement is a data type of

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Q. The instruction that pushes the general purpose registers, pointer and index registers on to the stack is

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Q. While executing the PUSH*A instruction, the stack pointer is decremented by

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Q. The statement that is true for the instruction POP*A is

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Q. The instruction that multiplies the content of AL with a signed immediate operand is

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Q. The instruction that represents the ‘rotate source, count’ is

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Q. In ‘Rotate source, count’ instructions, if the CF is equal to MSB of operand (source) then

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Q. The instruction that affects the flags is

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Q. A general protection exception is generated, if the value of

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