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Welcome to the Peripherals and Interfacing with 8086 MCQs Page

Dive deep into the fascinating world of Peripherals and Interfacing with 8086 with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Peripherals and Interfacing with 8086, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of Peripherals and Interfacing with 8086, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Peripherals and Interfacing with 8086 MCQs | Page 1 of 11

Q1.
The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
Discuss
Answer: (b).two dimensional
Q2.
If a location is selected, then all the bits in it are accessible using a group of conductors called
Discuss
Answer: (c).data bus
Q3.
To address a memory location out of N memory locations, the number of address lines required is
Discuss
Answer: (a).log N (to the base 2)
Q4.
If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
Discuss
Answer: (b).1024
Q5.
In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
Discuss
Answer: (d).odd address memory bank
Q6.
In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
Discuss
Answer: (b).even address memory bank
Q7.
In most of the cases, the method used for decoding that may be used to minimise the required hardware is
Discuss
Answer: (c).linear decoding
Q8.
To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
Discuss
Answer: (a).parallel
Discuss
Answer: (c).address is even and memory is in RAM
Q10.
If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
Discuss
Answer: (c).RAM and ROM
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