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Welcome to the Peripherals and Interfacing with 8086 MCQs Page

Dive deep into the fascinating world of Peripherals and Interfacing with 8086 with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Peripherals and Interfacing with 8086, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of Peripherals and Interfacing with 8086, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through Peripherals and Interfacing with 8086. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Peripherals and Interfacing with 8086. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Peripherals and Interfacing with 8086 MCQs | Page 1 of 11

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Q1.
The semiconductor memories are organised as __________ dimension(s) of array of memory locations.

a.

one dimensional

b.

two dimensional

c.

three dimensional

d.

none of the mentioned

Discuss
Answer: (b).two dimensional
Q2.
If a location is selected, then all the bits in it are accessible using a group of conductors called

a.

control bus

b.

address bus

c.

data bus

d.

either address bus or data bus

Discuss
Answer: (c).data bus
Q3.
To address a memory location out of N memory locations, the number of address lines required is

a.

log N (to the base 2)

b.

log N (to the base 10)

c.

log N (to the base e)

d.

log (2N) (to the base e)

Discuss
Answer: (a).log N (to the base 2)
Q4.
If the microprocessor has 10 address lines, then the number of memory locations it is able to address is

a.

512

b.

1024

c.

2048

d.

none of the mentioned

Discuss
Answer: (b).1024
Q5.
In static memory, the upper 8-bit bank of an available 16-bit memory chip is called

a.

upper address memory bank

b.

even address memory bank

c.

static upper memory

d.

odd address memory bank

Discuss
Answer: (d).odd address memory bank
Q6.
In static memory, the lower 8-bit bank of an available 16-bit memory chip is called

a.

lower address memory bank

b.

even address memory bank

c.

static lower memory bank

d.

odd address memory bank

Discuss
Answer: (b).even address memory bank
Q7.
In most of the cases, the method used for decoding that may be used to minimise the required hardware is

a.

absolute decoding

b.

non-linear decoding

c.

linear decoding

d.

none of the mentioned

Discuss
Answer: (c).linear decoding
Q8.
To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in

a.

parallel

b.

serial

c.

both serial and parallel

d.

neither serial nor parallel

Discuss
Answer: (a).parallel
Q9.
If (address line) Ao=0 then, the status of address and memory are

a.

address is even and memory is in ROM

b.

address is odd and memory is in ROM

c.

address is even and memory is in RAM

d.

address is odd and memory is in RAM

Discuss
Answer: (c).address is even and memory is in RAM
Q10.
If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be

a.

RAM

b.

ROM

c.

RAM and ROM

d.

ONLY RAM

Discuss
Answer: (c).RAM and ROM
Page 1 of 11

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