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Welcome to the 80286 80287 Microprocessor MCQs Page

Dive deep into the fascinating world of 80286 80287 Microprocessor with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of 80286 80287 Microprocessor, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of 80286 80287 Microprocessor, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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80286 80287 Microprocessor MCQs | Page 13 of 19

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Q121.
The 80286 executes LMSW instruction to enter into

a.

real addressing mode

b.

protected mode

c.

real addressing and protected modes

d.

none of the mentioned

Discuss
Answer: (b).protected mode
Q122.
The instruction that sets the zero flag, if the segment referred to, by the selector can be read is

a.

VERW

b.

VERR

c.

LSL

d.

LAR

Discuss
Answer: (b).VERR
Q123.
The instruction that sets the zero flag, if the segment referred to by the selector, can be written as

a.

VERW

b.

APRL

c.

LSL

d.

LAR

Discuss
Answer: (a).VERW
Q124.
The instruction that reads the descriptor access rights byte into the register is

a.

VERW

b.

APRL

c.

LSL

d.

LAR

Discuss
Answer: (d).LAR
Q125.
The instruction that reads the segment limit into the register, if privilege rules and descriptor type allow is

a.

VERW

b.

APRL

c.

LSL

d.

LAR

Discuss
Answer: (c).LSL
Q126.
The instruction that adjusts the RPL (Requested Privilege Level) of the selector, to the numeric maximum of current selector RPL value is

a.

LAR

b.

VERR

c.

LSL

d.

APRL

Discuss
Answer: (d).APRL
Q127.
Which of the following is a supporting chip of 80286?

a.

interrupt controller

b.

clock generator

c.

bus controller

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q128.
In minimum mode, the function of 80286 is

a.

data transfers to/from memory or I/O

b.

controls the data transfer of 80287

c.

controls the instruction execution of 80287

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q129.
The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch and data bus cycles is

a.

COD

b.

INTA (active low)

c.

M/IO (active low)

d.

All of the mentioned

Discuss
Answer: (d).All of the mentioned
Q130.
By adding which of the following, the minimum mode of 80286 gives the multibus interface of 80286?

a.

bus controller

b.

bus arbiter

c.

interrupt controller

d.

all of the mentioned

Discuss
Answer: (b).bus arbiter
Page 13 of 19

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