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Welcome to the DMA MCQs Page

Dive deep into the fascinating world of DMA with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of DMA, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of DMA, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through DMA. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of DMA. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

DMA MCQs | Page 1 of 7

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Q1.
In direct memory access mode, the data transfer takes place

a.

directly

b.

indirectly

c.

directly and indirectly

d.

none of the mentioned

Discuss
Answer: (a).directly
Q2.
In 8257 (DMA), each of the four channels has

a.

a pair of two 8-bit registers

b.

a pair of two 16-bit registers

c.

one 16-bit register

d.

one 8-bit register

Discuss
Answer: (b).a pair of two 16-bit registers
Q3.
The common register(s) for all the four channels of 8257 are

a.

DMA address register

b.

terminal count register

c.

mode set register and status register

d.

none of the mentioned

Discuss
Answer: (c).mode set register and status register
Q4.
In 8257 register format, the selected channel is disabled after the terminal count condition is reached when

a.

auto load is set

b.

auto load is reset

c.

TC STOP bit is reset

d.

TC STOP bit is set

Discuss
Answer: (d).TC STOP bit is set
Q5.
The IOR (active low) input line acts as output in

a.

slave mode

b.

master mode

c.

master and slave mode

d.

none of the mentioned

Discuss
Answer: (b).master mode
Q6.
The IOW (active low) in its slave mode loads the contents of data bus to

a.

8-bit mode register

b.

upper/lower byte of 16-bit DMA address register

c.

terminal count register

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q7.
The pin that disables all the DMA channels by clearing the mode registers is

a.

MARK

b.

CLEAR

c.

RESET

d.

READY

Discuss
Answer: (c).RESET
Q8.
The pin that requests the access of the system bus is

a.

HLDA

b.

HRQ

c.

ADSTB

d.

none of the mentioned

Discuss
Answer: (b).HRQ
Q9.
The pin that is used to write data to the addressed memory location, during DMA write operation is

a.

MEMR (active low)

b.

AEN

c.

MEMW (active low)

d.

IOW (active low)

Discuss
Answer: (c).MEMW (active low)
Q10.
The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is

a.

AEN

b.

ADSTB

c.

TC

d.

none of the mentioned

Discuss
Answer: (b).ADSTB
Page 1 of 7

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