Computer Architecture Multiple choice Questions and Answers-GATE cse question paper

71.	A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
a.	INTA is active
b.	HOLD is active
c.	READY is active
d.	None of these

Answer: (a).INTA is active

72.	In 8085, which of the following modifies the program counter ?
a.	Only PCHL instruction
b.	Only ADD instructions
c.	Only JMP and CALL instructions
d.	All instructions

Answer: (d).All instructions

73.	The 2' s complement representation of the decimal value - 15 is
a.	1111
b.	11111
c.	111111
d.	10001

Answer: (d).10001

74.	Sign extension is a step in
a.	floating point multiplication
b.	signed 16 bit integer addition
c.	arithmetic left shift
d.	converting a signed integer from one size to another

Answer: (d).converting a signed integer from one size to another

75.	In 2' s complement addition, overflow
a.	is flagged whenever there is carry from sign bit addition
b.	cannot occur when a positive value is added to a negative value
c.	is flagged when the carries from sign bit and previous bit match
d.	none of the above

Answer: (b).cannot occur when a positive value is added to a negative value

76.	In the absolute addressing mode
a.	the operand is inside the instruction
b.	the address of the operand is inside the instruction
c.	the register containing address of the operand is specified inside the instruction
d.	the location of the operand is implicit

Answer: (b).the address of the operand is inside the instruction

77.	Consider the following multiplexer where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is the output of the multiplexer. EN is the enable input. The function f(x, y, z) implemented by the circuit is :
a.	xyz'
b.	xy + z
c.	x + z
d.	None of these

Answer: (a).xyz'

78.	What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program? MVI L, 5DH MVI L, 6BH MOV A, H ADD L
a.	AC = 0 and CY = 0
b.	AC = 1 and CY = 1
c.	AC = 1 and CY = 0
d.	AC = 0 and CY = 0

Answer: (c).AC = 1 and CY = 0

79.	The performance of a pipelined processor suffers if
a.	the pipeline stages have different delays
b.	consecutive instructions are dependent on each other
c.	the pipeline stages share hardware resources
d.	all of the above

Answer: (d).all of the above

80.	Horizontal microprogramming :
a.	does not require use of signal decoders
b.	results in larger sized microinstructions than vertical microprogramming
c.	uses one bit for each control signal
d.	all of the above

Answer: (d).all of the above