# Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

### Computer Architecture MCQs | Page 8 of 20

Q71.
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
Q72.
In 8085, which of the following modifies the program counter ?
Q73.
The 2' s complement representation of the decimal value - 15 is
Q74.
Sign extension is a step in
Answer: (d).converting a signed integer from one size to another
Q75.
In 2' s complement addition, overflow
Answer: (b).cannot occur when a positive value is added to a negative value
Q76.
Q77.
Consider the following multiplexer where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is the output of the multiplexer. EN is the enable input.
The function f(x, y, z) implemented by the circuit is :
Q78.
What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program?

MVI L, 5DH
MVI L, 6BH
MOV A, H
Answer: (c).AC = 1 and CY = 0
Q79.
The performance of a pipelined processor suffers if