| 21. | A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required? |
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Answer: (b).3
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| 22. | Which are the essential prime implicants of the following Boolean function? f(a, b, c) = a'c + ac' + b'c |
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Answer: (a).a'c and ac'
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| 23. | Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware ? |
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Answer: (a).R to X, 1 to Y, T to Z
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| 24. | A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic. |
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Answer: (a).4 time units
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| 25. | Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is |
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Answer: (c).Θ(n)
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| 26. | A 1-input, 2-output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds. zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10. nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01. What is the minimum number of states required in the state transition graph of the above circuit? |
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Answer: (a).5
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| 27. | Let f(A, B) = A' + B. Simplified expression for function f(f(x + y, y)z) is : |
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Answer: (c).xy' + z
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| 28. | Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is: |
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Answer: (d).0, 8, 12, 14, 15, 7, 3, 1, 0
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| 29. | A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays. |
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Answer: (a).0110110...
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| 30. | Consider the operations f(X, Y, Z) = X'YZ + XY' + Y'Z' and g(X′, Y, Z) = X′YZ + X′YZ′ + XY. Which one of the following is correct? |
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Answer: (b).Only {f} is functionally complete
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