# Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

### Computer Architecture MCQs | Page 20 of 20

Q191.
In an SR latch made by cross coupling two NAND gates, If both S and R inputs are set to 0, then it will result in
Answer: (c).q = 1, q’ = 1
Q192.
The purpose of latch feedback is?
Q193.
The minimum number of D flip – flops needed to design a mod – 258 counter is
Q194.
A 10 – bit Asynchronous counter is having initial value 0 1 0 0 0 1 1 1 1 1. How many flip flops are complemented at next clock?

a.

1

b.

5

c.

6

d.

7

Q195.
A sequential circuit is having one input and 2 states; The clock is initially in state A. It remains in the same state as long as (x=0) (i.e., input =0). If the input is 1, it switches to the state B and remains there as long as input is 0. On receiving 1 it switches back to state A. If it is realized with D – FF. what is the expression for D FF?
Q196.
How many 3 – to – 8 line decoders with an enable input are needed to construct a 6 – to – 64 line decoder without using any other logic gates?

a.

7

b.

8

c.

9

d.

10

Q197.
Let the 3 variable function f (a, b, c) = Σ (0, 1, 4, 5,7) is realized with 4x1 mux. The select line S₁ & S₀ are connected with A, B. What will be the connections for data inputs?
Q198.
Consider a 3-variable function; f(A, B,C) = S (0, 1, 2, 4). It is realized with a 4x1 multiplexer; select lines S₁ S₀ are taken as B, C. Later it was found that select lines have to be interchanged w.r.t the data line in both terminations, Identify the correct statements.
Answer: (d).No need to change any input terminations
Q199.
Consider a binary channel which has 1 – input and 1 – output initially the input is reproduced at output until two consecutive zero’s are received from then onwards output is the bit – wise complement of input complement continuous until two consecutive 1’s are received at input, from then onwards it repeats the behaviour. What will be the minimum number of states in this binary channel.

a.

2

b.

4

c.

8

d.

12

Q200.
A sequence machine is supposed to receive block of 0’s & 1’s the correct operation required 1’s, number of 1’s in 1st block must be odd and number of 0’s in 0’s block must be even. Any violation indicated by machine outputs 1 against 1st bit of opposite block. What will be minimum number of states in the sequence machine?

a.

2

b.

3

c.

4

d.

5