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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 6 of 20

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Q51.
The complement of the function F = (A + B’)(C’ + D)(B’ + C) is:

a.

A’B + CD’ + BC'

b.

AB’ + C’D + B’C

c.

AB’ + CD’ + BC

d.

AB + BC + CD

Discuss
Answer: (a).A’B + CD’ + BC'
Q52.
To put the 8085 microprocessor in the wait state

a.

lower the-HOLD input

b.

lower the READY input

c.

raise the HOLD input

d.

raise the READY input

Discuss
Answer: (b).lower the READY input
Q53.
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that

a.

T1 <= T2

b.

T1 >= T2

c.

T1 < T2

d.

T1 is T2 plus the time taken for one instruction fetch cycle

Discuss
Answer: (b).T1 >= T2
Q54.
The 8085 microprocessor responds to the presence of an interrupt

a.

As soon as the TRAP pin becomes 'high'

b.

By checking the TRAP pin for 'high' status at the end of each instruction fetch

c.

By checking the TRAP pin for 'high' status at the end of the execution of each instruction

d.

By Checking the TRAP pin for 'high' status at regular intervals

Discuss
Answer: (c).By checking the TRAP pin for 'high' status at the end of the execution of each instruction
Q55.
The most appropriate matching for the following pairs

X: Indirect addressing 1 : Loops

Y: Immediate addressing 2 : Pointers

Z: Auto decrement addressing 3: Constants

is

a.

X-3, Y-2, Z-1

b.

X-I, Y-3, Z-2

c.

X-2, Y-3, Z-1

d.

X-3, Y-l, Z-2

Discuss
Answer: (c).X-2, Y-3, Z-1
Q56.
The simultaneous equations on the Boolean variables x, y, z and w, have the following solution for x, y, z and w, respectively.

a.

0 1 0 0

b.

1 1 0 1

c.

1 0 1 1

d.

1 0 0 0

Discuss
Answer: (c).1 0 1 1
Q57.
Which function does NOT implement the Karnaugh map given below?

a.

a

b.

b

c.

c

d.

d

Discuss
Answer: (d).d
Q58.
The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

a.

1, 0

b.

1, 1

c.

0, 0

d.

0,1

Discuss
Answer: (a).1, 0
Q59.
Consider the values A = 2.0 x 10^30, B =-2.0 x 10^30, C= 1.0, and the sequence

X: = A + B Y: = A + C
X: = X + C Y: = Y + B

executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be

a.

X = 1.0, Y = 1.0

b.

X = 1.0, Y = 0.0

c.

X = 0.0, Y = 1.0

d.

X = 0.0, Y = 0.0

Discuss
Answer: (b).X = 1.0, Y = 0.0
Q60.
A low memory can be connected to 8085 by using

a.

INTER

b.

RESET IN

c.

HOLD

d.

READY

Discuss
Answer: (d).READY
Page 6 of 20

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