Q. Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?

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Q. For a pipelined CPU with a single ALU, consider the following situations

1. The j + 1-st instruction uses the result of the j-th instruction
as an operand
2. The execution of a conditional jump instruction
3. The j-th and j + 1-st instructions require the ALU at the same
time

Which of the above can cause a hazard ?

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Q. Consider the grammar rule E → E1 - E2 for arith­metic expressions. The code generated is targeted to a CPU having a single user register. The sub­traction operation requires the first operand to be in the register. If E1 and E2 do not have any com­mon sub expression, in order to get the shortest possible code

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Q. If 73x (in base-x number system) is equal to 54y (in base-y number system), the possible values of x and y are

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Q. Which of the following addressing modes are suitable for program relocation at run time ?

(i) Absolute addressing
(ii) Based addressing
(iii) Relative addressing
(iv) Indirect addressing

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Q. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is

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Q. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

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Q. Spatial locality refers to the problem that once a location is referenced

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Q. The Principle of locality justifies the use of

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Q. A system that has a lot of crashes, data should be written to the disk using?

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Q. Which addressing mode is suitable for a high-level language statement?

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Q. Which memory unit has the lowest access time?

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Q. In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is

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Q. A 32-bit address bus allows access to a memory of capability

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Q. Pipelining improves CPU performance due to?

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Q. The system bus consists of

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Q. An instruction cycle refers to

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Q. A hardware interrupt is

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Q. Which of the following is not involved in a memory write operation?

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Q. To prevent signals from colliding on the bus, ……………….. Prioritize access to memory by I/o channels and processors.

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