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91. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is
a. 1100 0100
b. 1001 1100
c. 1010 0101
d. 1101 0101
Answer: (a).1100 0100

92. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be
a. 120.4 microseconds
b. 160.5 microseconds
c. 165.5 microseconds
d. 590.0 microseconds
Answer: (c).165.5 microseconds

93. Spatial locality refers to the problem that once a location is referenced
a. It will not be referenced again
b. It will be referenced again
c. A nearby location will be referenced soon
d. None of the above
Answer: (c).A nearby location will be referenced soon

94. The Principle of locality justifies the use of
a. Interrupts
b. Threads
c. DMA
d. Cache memory
Answer: (d).Cache memory

95. A system that has a lot of crashes, data should be written to the disk using?
a. write – through
b. write – back
c. Both a and b
d. None of the above
Answer: (b).write – back

96. Which addressing mode is suitable for a high-level language statement?
a. Auto increment
b. Indexed
c. Displacement
d. Auto decrement
Answer: (d).Auto decrement

97. Which memory unit has the lowest access time?
a. Cache
b. Registers
c. Magnetic disk
d. Main memory
Answer: (b).Registers

98. In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is
a. 0
b. 1
c. Pointer
d. Off - Set
Answer: (b).1

99. A 32-bit address bus allows access to a memory of capability
a. 64 MB
b. 16 MB
c. 1 GB
d. 4 GB
Answer: (d).4 GB

100. Pipelining improves CPU performance due to?
a. Reduced memory access time
b. Increased clock speed
c. The introduction of parallelism
d. Additional functional units
Answer: (c).The introduction of parallelism