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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 10 of 20

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Q91.
Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is

a.

1100 0100

b.

1001 1100

c.

1010 0101

d.

1101 0101

Discuss
Answer: (a).1100 0100
Q92.
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

a.

120.4 microseconds

b.

160.5 microseconds

c.

165.5 microseconds

d.

590.0 microseconds

Discuss
Answer: (c).165.5 microseconds
Q93.
Spatial locality refers to the problem that once a location is referenced

a.

It will not be referenced again

b.

It will be referenced again

c.

A nearby location will be referenced soon

d.

None of the above

Discuss
Answer: (c).A nearby location will be referenced soon
Q94.
The Principle of locality justifies the use of

a.

Interrupts

b.

Threads

c.

DMA

d.

Cache memory

Discuss
Answer: (d).Cache memory
Q95.
A system that has a lot of crashes, data should be written to the disk using?

a.

write – through

b.

write – back

c.

Both a and b

d.

None of the above

Discuss
Answer: (b).write – back
Q96.
Which addressing mode is suitable for a high-level language statement?

a.

Auto increment

b.

Indexed

c.

Displacement

d.

Auto decrement

Discuss
Answer: (d).Auto decrement
Q97.
Which memory unit has the lowest access time?

a.

Cache

b.

Registers

c.

Magnetic disk

d.

Main memory

Discuss
Answer: (b).Registers
Q98.
In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is

a.

0

b.

1

c.

Pointer

d.

Off - Set

Discuss
Answer: (b).1
Q99.
A 32-bit address bus allows access to a memory of capability

a.

64 MB

b.

16 MB

c.

1 GB

d.

4 GB

Discuss
Answer: (d).4 GB
Q100.
Pipelining improves CPU performance due to?

a.

Reduced memory access time

b.

Increased clock speed

c.

The introduction of parallelism

d.

Additional functional units

Discuss
Answer: (c).The introduction of parallelism
Page 10 of 20

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