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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 5 of 20

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Q41.
Using Booth's Algorithm for multiplication, the multiplier -57 will be recoded as

a.

0 -1 0 0 1 0 0 -1

b.

1 1 0 0 0 1 1 1

c.

0 -1 0 0 1 0 0 0

d.

0 1 0 0 -1 0 0 1

Discuss
Answer: (a).0 -1 0 0 1 0 0 -1
Q42.
How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

a.

134

b.

133

c.

124

d.

123

Discuss
Answer: (d).123
Q43.
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is

a.

1

b.

2

c.

4

d.

5

Discuss
Answer: (c).4
Q44.
Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

a.

Θ(1)

b.

Θ(Log (n))

c.

Θ(√ n)

d.

Θ(n)

Discuss
Answer: (b).Θ(Log (n))
Q45.
Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________

a.

-1

b.

2

c.

1

d.

-2

Discuss
Answer: (a).-1
Q46.
Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation. Then X −Y is _________

a.

1

b.

2

c.

3

d.

0

Discuss
Answer: (a).1
Q47.
The addition of 4-bit, two's complement, binary numbers 1101 and 0100 results in

a.

0001 and an overflow

b.

1001 and no overflow

c.

0001 and no overflow

d.

1001 and an overflow

Discuss
Answer: (c).0001 and no overflow
Q48.
Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation ?

a.

11, 00

b.

01, 10

c.

10, 01

d.

00, 11

Discuss
Answer: (d).00, 11
Q49.
The following bit pattern represents a floating point number in IEEE 754 single precision format 1 10000011 101000000000000000000000 The value of the number in decimal form is

a.

-10

b.

-13

c.

-26

d.

None of these

Discuss
Answer: (c).-26
Q50.
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:

a.

1, 1, 0

b.

1, 0, 0

c.

0, 1, 0

d.

1, 0, 1

Discuss
Answer: (b).1, 0, 0
Page 5 of 20

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