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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 9 of 20

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Q81.
Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?

a.

11100111

b.

11100100

c.

11010111

d.

11011011

Discuss
Answer: (a).11100111
Q82.
For a pipelined CPU with a single ALU, consider the following situations

1. The j + 1-st instruction uses the result of the j-th instruction
as an operand
2. The execution of a conditional jump instruction
3. The j-th and j + 1-st instructions require the ALU at the same
time

Which of the above can cause a hazard ?

a.

1 and 2 only

b.

2 and 3 only

c.

3 only

d.

All of above

Discuss
Answer: (d).All of above
Q83.
The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz') is 4. What are the minimum possible literal counts of the product-of-sum and sum-of-product representations respectively of the function given by the following Karnaugh map ? Here, X denotes "don't care".

a.

(11, 9)

b.

(9, 13)

c.

(9, 10)

d.

(11, 11)

Discuss
Answer: (c).(9, 10)
Q84.
Consider the ALU shown below. If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction respectively) ?

a.

A + B, and A - B, but not A + 1

b.

A + B, and A + 1, but not A - B

c.

A + B, but not A - B, or A + 1

d.

A + B, and A - B, and A + 1

Discuss
Answer: (a).A + B, and A - B, but not A + 1
Q85.
Consider the following circuit composed of XOR gates and non-inverting buffers. The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?

a.

1

b.

2

c.

3

d.

4

Discuss
Answer: (d).4
Q86.
Consider the grammar rule E → E1 - E2 for arith­metic expressions. The code generated is targeted to a CPU having a single user register. The sub­traction operation requires the first operand to be in the register. If E1 and E2 do not have any com­mon sub expression, in order to get the shortest possible code

a.

E1 should be evaluated first

b.

E2 should be evaluated first

c.

Evaluation of E1 and E2 should necessarily be interleaved

d.

Order of evaluation of E1 and E2 is of no consequence

Discuss
Answer: (b).E2 should be evaluated first
Q87.
If 73x (in base-x number system) is equal to 54y (in base-y number system), the possible values of x and y are

a.

8, 16

b.

10, 12

c.

9, 13

d.

8, 11

Discuss
Answer: (d).8, 11
Q88.
Which of the following addressing modes are suitable for program relocation at run time ?

(i) Absolute addressing
(ii) Based addressing
(iii) Relative addressing
(iv) Indirect addressing

a.

(i) and (iv)

b.

(i) and (ii)

c.

(ii) and (iii)

d.

(i), (ii) and (iv)

Discuss
Answer: (c).(ii) and (iii)
Q89.
Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0, as shown below. To complete the circuit, the input X should be

a.

Q2'

b.

Q2 + Q1

c.

(Q1 ⊕ Q2)'

d.

Q1 ⊕ Q2

Discuss
Answer: (d).Q1 ⊕ Q2
Q90.
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.
How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

a.

10, 3, 1024

b.

8, 5, 256

c.

5, 8, 2048

d.

10, 3, 512

Discuss
Answer: (a).10, 3, 1024
Page 9 of 20

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