Q. The system bus consists of

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Q. An instruction cycle refers to

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Q. A hardware interrupt is

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Q. Which of the following is not involved in a memory write operation?

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Q. To prevent signals from colliding on the bus, ……………….. Prioritize access to memory by I/o channels and processors.

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Q. …………… improve system performance by temporarily storing data during transfers s/w devices or processers that operate at different speeds.

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Q. Addressing mode is …………………

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Q. Which of the following is not a valid class of interrupts?
1) Program
2) Timer
3) I/o
4) Hardware failure

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Q. System calls are usually invoked by using

1) An indirect jump
2) A software interrupt
3) Polling
4) A privileged instruction

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Q. Which of the following holds data and processing instructions temporarily until the CPU needs it??

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Q. Which of the following register processors used for fetch and execute operations?
1) Program counter
2) Instruction register
3) Address register

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Q. Microinstruction length is determined by ………………..

1) The maximum number of simultaneous micro-operations that must be specified
2) The way in which the control information is represented or encoded
3) The way in which the next microinstruction address is specified

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Q. ID catching system, the memory reference made in any short time integral tends to use only a small fraction of the total memory?

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Q. The word length of a CPU is defined as

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Q. The register which holds the address of the locating to or from which data are to be transferred is known as

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Q. Which one is required while establishing the communication link between CPU and peripherals?

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Q. Which of the following data transfer modes takes relatively more time?

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Q. Halt operation comes under ………

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Q. The CPU initializes the DMA by sending ………

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Q. In four – address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code)

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