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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 14 of 20

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Q131.
The bus system of a machine has the following propagation delay times 40 ns for the signals to propagate through the multiplexers, 90ns to perform the ADD operating in the ALU, 30ns delay in the destination decoder, and 20ns to store the data into the destination register. What is the minimum cycle time that can be used for the clock?

a.

120ns

b.

150ns

c.

960ns

d.

180ns

Discuss
Answer: (b).150ns
Q132.
The sequence of events that happen during a typical fetch operation is ?

a.

PC → Mar →Memory → MOR → IR

b.

PC → Memory → MDR → IR

c.

PC → Memory → IR

d.

PC → Mar → Memory → IR

Discuss
Answer: (a).PC → Mar →Memory → MOR → IR
Q133.
In a fully associative cache memory consisting of 256 cache lines of 16 bytes each, a tag field is of 14 bits. Determine the size of cache memory and main memory.

a.

2KB and 128 KB

b.

4kB and 256KB

c.

8KB and 1MB

d.

None of the above

Discuss
Answer: (b).4kB and 256KB
Q134.
If doubling the cache line length reduces the miss rate to 3 percent, by how much it reduces the average memory access time?

a.

27.1ns

b.

25.75ns

c.

22.2ns

d.

4.85ns

Discuss
Answer: (a).27.1ns
Q135.
Consider the following register – transfer language:

R₃ ← R₂+ M[R₁ + R₂]

Where R₁, R₂ are the CPU registers and M is a memory location in primary memory, which addressing mode is suitable for above register transfer language?

a.

Immediate

b.

Indexed

c.

Direct

d.

Displacement

Discuss
Answer: (b).Indexed
Q136.
Booth′s algorithm is used in floating – point

a.

Addition

b.

Subtraction

c.

Multiplication

d.

Division

Discuss
Answer: (c).Multiplication
Q137.
A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a through put of

a.

1⁄3

b.

1⁄7

c.

7

d.

3

Discuss
Answer: (a).1⁄3
Q138.
What is the control unit’s function in the CPU?

a.

To decode program instructions

b.

To transfer data to primary storage

c.

To perform logical operations

d.

To store program instructions

Discuss
Answer: (a).To decode program instructions
Q139.
Consider on (n+k) bit instruction with a k-bit opcode and single n-bit address. Then this instruction allows…………….. Operations and …………… addressable memory cells.?

a.

A

b.

B

c.

C

d.

D

Discuss
Answer: (c).C
Q140.
The following diagram shows, which addressing mode?

a.

Immediate addressing mode

b.

Indirect addressing mode

c.

Extended addressing mode

d.

None of the above

Discuss
Answer: (c).Extended addressing mode
Page 14 of 20

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