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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of UGC CBSE NET Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within UGC CBSE NET Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of UGC CBSE NET Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 7 of 16

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Q61.
Which of the following 8085 microprocessor hardware interrupt has the lowest priority?

a.

RST 6.5

b.

RST 7.5

c.

TRAP

d.

INTR

Discuss
Answer: (d).INTR
Q62.
A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?

a.

0.64

b.

0.96

c.

2.00

d.

0.32

Discuss
Answer: (d).0.32
Q63.
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?

a.

0.06%

b.

0.12%

c.

1.2%

d.

2.5%

Discuss
Answer: (b).0.12%
Q64.
A CPU handles interrupt by executing interrupt service subroutine.................

a.

by checking interrupt register after execution of each instruction

b.

by checking interrupt register at the end of the fetch cycle

c.

whenever an interrupt is registered

d.

by checking interrupt register at regular time interval

Discuss
Answer: (a).by checking interrupt register after execution of each instruction
Q65.
What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below:

a.

11

b.

10

c.

01

d.

00

Discuss
Answer: (d).00
Q66.
Which one of the following set of gates is best suited for ‘parity’ checking and ‘parity’ generation?

a.

AND, OR, NOT

b.

NAND, NOR

c.

EX-OR, EX-NOR

d.

None of the above

Discuss
Answer: (c).EX-OR, EX-NOR
Q67.
What type of logic circuit is represented by the figure shown below?

a.

XOR

b.

XNOR

c.

XAND

d.

XNAND

Discuss
Answer: (b).XNOR
Q68.
The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio:

Where n → no. of tasks
tn → time of completion of each task
k → no. of segments of pipeline
tp → clock cycle time
S → speed up ratio

a.

A

b.

B

c.

C

d.

D

Discuss
Answer: (a).A
Q69.
................ refers to the discrepancy among a computed, observed or measured value and the true specified or theoretically correct values.

a.

Fault

b.

Failure

c.

Defect

d.

Error

Discuss
Answer: (d).Error
Q70.
Which logic family dissipates the minimum power ?

a.

DTL

b.

TTL

c.

ECL

d.

CMOS

Discuss
Answer: (d).CMOS
Page 7 of 16

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