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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of UGC CBSE NET Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within UGC CBSE NET Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of UGC CBSE NET Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 10 of 16

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Q91.
Identify the devices given below with their IC numbers :

(i) USART                                 (a) 8251
(ii) Micro controller                (b) 8051
(iii) Interrupt controller         (c) 8259
(iv) DMA controller                 (d) 8257

      (i)   (ii)    (iii) (iv)

a.

(a)  (b)   (c)  (d)

b.

(b)  (a)   (d)  (c)

c.

(c)  (d)   (a)  (b)

d.

(d)  (a)   (b)  (c)

Discuss
Answer: (a).(a)  (b)   (c)  (d)
Q92.
On receiving an interrupt from an I/O device, the CPU

a.

halts for predetermined time.

b.

branches off to the interrupt service routine after completion of the current instruction.

c.

branches off to the interrupt service routine immediately.

d.

hands over control of address bus and data bus to the interrupting device.

Discuss
Answer: (b).branches off to the interrupt service routine after completion of the current instruction.
Q93.
Consider a logical address space of 8 pages of 1024 words mapped with memory of 32 frames. How many bits are there in the physical address?

a.

9 bits

b.

11 bits

c.

13 bits

d.

15 bits

Discuss
Answer: (d).15 bits
Q94.
CPU does not perform the operation

a.

data transfer

b.

logic operation

c.

arithmetic operation

d.

all of the above

Discuss
Answer: (d).all of the above
Q95.
A chip having 150 gates will be classified as

a.

SSI

b.

MSI

c.

LSI

d.

VLSI

Discuss
Answer: (b).MSI
Q96.
A latch is constructed using two cross-coupled

a.

AND and OR gates

b.

AND gates

c.

NAND and NOR gates

d.

NAND gates

Discuss
Answer: (d).NAND gates
Q97.
An astable multivibrator has

a.

one stable state

b.

two stable states

c.

no stable states

d.

none of these

Discuss
Answer: (c).no stable states
Q98.
The register or main memory location which contains the effective address of the operand is known as

a.

pointer

b.

special location

c.

indexed register

d.

None of the above

Discuss
Answer: (a).pointer
Q99.
The logic expression for the output of the circuit shown in the figure is

a.

A’C’+B’C’+CD

b.

AC’+BC’+C’D

c.

ABC+C’D’

d.

A’B’+B’C’+C’D’

Discuss
Answer: (c).ABC+C’D’
Q100.
Advantage of synchronous sequential circuits over asynchronous ones is

a.

faster operation

b.

ease of avoiding problems due to hazard

c.

lower hardware requirement

d.

better noise immunity

Discuss
Answer: (a).faster operation
Page 10 of 16

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