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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of UGC CBSE NET Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within UGC CBSE NET Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of UGC CBSE NET Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 3 of 16

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Q21.
Which of the following statements is not true?

a.

MPI_lsend and MPI_Irecv are non-blocking message passing routines of MPI

b.

MPI_lssend and MPI_Ibsend are non-blocking message passing routines of MPI

c.

MPI_Send and MPI_Recv are non-blocking message passing routines of MPI

d.

MPI_Ssend and MPI_Bsend are blocking message passing routines of MPI

Discuss
Answer: (a).MPI_lsend and MPI_Irecv are non-blocking message passing routines of MPI
Q22.
 Consider the following statements :

(a) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(b) Optimal Boolean expressions may not correspond to simplest networks.
(c) Choosing essential blocks first in a Karnaugh map and then greedily choosing the largest remaining blocks to cover may not give an optimal expression.
Which of these statement(s) is/ are correct

a.

(a) only

b.

(b) only

c.

(a) and (b)

d.

(a), (b) and (c)

Discuss
Answer: (d).(a), (b) and (c)
Q23.
Consider a full adder with the following input values :

(a) x=1, y=0 and Ci(carry input) = 0
(b) x=0, y=1 and Ci = 1
Compute the values of S(sum) and C0 (carry output) for the above input values.

a.

S=1 , C0= 0 and S=0 , C0= 1

b.

S=0 , C0= 0 and S=1 , C0​= 1

c.

S=1 , C0= 1 and S=0 , C0​= 0

d.

S=0 , C0= 1 and S=1 , C0​= 0

Discuss
Answer: (a).S=1 , C0= 0 and S=0 , C0= 1
Q24.
In the case of parallelization, Amdahl's law states that if P is the proportion of the program that can be made parallel and (1 - P) is the proportion that cannot be parallelized , then the maximum speed that can be achieved by using N processors is

a.

1/ (1-P) + (N.P)

b.

1/ (N-1) P +P

c.

1/ (1-P)  + P/N

d.

1/ P + ((1-P)/N)

Discuss
Answer: (c).1/ (1-P)  + P/N
Q25.
Which of the following statements is incorrect for Parallel Virtual Machine (PVM)?

a.

The PVM Communication model provides asynchronous blocking send, asynchronous blocking receive and non-blocking receive function

b.

Message buffers are allocated dynamically

c.

The PVM communication model assumes that any task that can send a message to any other PVM task and that there is no limit to the size or number of such messages

d.

In PVM Model, the message order is not preserved

Discuss
Answer: (d).In PVM Model, the message order is not preserved
Q26.
Which of the following is not valid with reference to Message Passing Interface (MPI) ?

a.

MPI can run on any hardware platform

b.

The programming model is a distributed memory model

c.

All parallelism is implicit

d.

MPI - Comm - Size returns the total number of MPI processes in specified communication

Discuss
Answer: (c).All parallelism is implicit
Q27.
For the 8 - bit word 00111001, the check bits stored with it would be 0111. Suppose when the word is read from memory, the check bits are calculated to be 1101. What is the data word that was read from memory?

a.

10011001

b.

00011001

c.

00111000

d.

11000110

Discuss
Answer: (b).00011001
Q28.
Consider a 32 - bit microprocessor, with a 16 - bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor?

a.

8x10^6 bytes/sec

b.

4x10^6 bytes/sec

c.

16x10^6 bytes/sec

d.

4x10^9 bytes/sec

Discuss
Answer: (b).4x10^6 bytes/sec
Q29.
The RST 7 instruction in 8085 microprocessor is equivalent to :

a.

CALL 0010  H

b.

CALL 0034  H

c.

CALL 0038  H

d.

CALL 003C  H

Discuss
Answer: (c).CALL 0038  H
Q30.
The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used?

a.

500 Kbytes/sec

b.

2.2 Mbytes/sec

c.

125 Kbytes/sec

d.

250 Kbytes/sec

Discuss
Answer: (d).250 Kbytes/sec
Page 3 of 16

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