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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of UGC CBSE NET Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within UGC CBSE NET Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of UGC CBSE NET Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 6 of 16

Q51.
In ............... addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.
Discuss
Answer: (b).Register indirect
Q52.
Which of the following is a sequential circuit?
Discuss
Answer: (c).Counter
Q53.
8085 microprocessor has ............. hardware interrupts.

a.

2

b.

3

c.

4

d.

5

Discuss
Answer: (d).5
Q54.
Which of the  following in 8085 microprocessor performs
HL = HL + DE ?
Discuss
Answer: (a).DAD D
Q55.
The Register that stores all interrupt requests is:
Discuss
Answer: (c).Interrupt request register
Q56.
The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.
Discuss
Answer: (d).Displacement
Q57.
In ............. method, the word is written to the block in both the cache and main memory, in parallel.
Discuss
Answer: (a).Write through
Q58.
A Multicomputer with 256 CPUs is organized as 16x16 grid. What is the worst case delay (in hops) that a message might have to take?
Discuss
Answer: (d).30
Q59.
What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions?

Mov al, 15
Mov ah, 15
Xor al, al
Mov cl, 3
Shr ax, cl
Discuss
Answer: (c).01E0 h
Q60.
What will be the output at PORT1 if the following program is executed?

MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT
Discuss
Answer: (b).82H
Page 6 of 16

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