Q. The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used?

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Q. The number of flip-flops required to design a modulo - 272 counter is :

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Q. Consider a uniprocessor system where new processes arrive at an average of five processes per minute and each process needs an average of 6 seconds of service time. What will be the CPU utilization ?

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Q. The advantage of _______ is that it can reference memory without paying the price of having a full memory address in the instruction.

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Q. The output of a sequential circuit depends on

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Q. Which of the following flip-flops is free from race condition ?

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Q. Pipelining improves performance by:

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Q. A multiplexer is a logic circuit that

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Q. 8-bit 1’s complement form of –77.25 is

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Q. ECL is the fastest of all logic families. High Speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ...............

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Q. A binary 3-bit down counter uses J-K flip-flops, FFi with inputs Ji, Ki and outputs Qi, i=0,1,2 respectively. The minimized expression for the input from following, is

I. J0=K0=0
II. J0=K0=1
III. J1=K1=Q0
IV. J1=K1=Q'0
V. J2=K2=Q1Q0
Vl. J2=K2=Q'1Q'0

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Q. Which of the following is an interrupt according to temporal relationship with system clock?

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Q. Match the following:

Addressing Mode      Location of operand
a. Implied                      i. Registers which are in CPU
b. Immediate                 ii. Register specifies the address
of the operand
c. Register                     iii. Specified in the register
d. Register Indirect      iv. Specified implicitly in the
definition of instruction

Codes:
     a   b   c  d

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Q. In 8085 microprocessor, the digit 5 indicates that the microprocessor needs

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Q. In 8085, which of the following performs: load register pair immediate operation?

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Q. The content of the accumulator after the execution of the following 8085 assembly language program, is

MVI A, 35H
MOV B, A
STC
CMC
RAR
XRA B

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Q. A ripple counter is a (n):

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Q. 8085 microprocessor has ............... bit ALU.

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Q. The register that stores the bits required to mask the interrupts is ................

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Q. Which of the following in 8085 microprocessor performs

HL = HL + HL ?

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