Q. On receiving an interrupt from an I/O device, the CPU

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Q. Consider a logical address space of 8 pages of 1024 words mapped with memory of 32 frames. How many bits are there in the physical address?

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Q. CPU does not perform the operation

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Q. A chip having 150 gates will be classified as

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Q. A latch is constructed using two cross-coupled

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Q. An astable multivibrator has

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Q. The register or main memory location which contains the effective address of the operand is known as

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Q. Advantage of synchronous sequential circuits over asynchronous ones is

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Q. What is the transitive voltage for the voltage input of a CMOS operating from 10V supply?

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Q. The highest noise margin is offered by

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Q. The characteristic equation of a JK flip flop is:

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Q. In order to implement a n variable switching function, a MUX must have:

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Q. A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential machine is:

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Q. In which addressing mode the operand is given explicitly in the instruction itself?

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Q. The characteristic equation of D flip-flop is:

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Q. If 4 input multiplexers drive a 4 input multiplexer, we get a:

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Q. In which addressing mode, the effective address of the operand is generated by adding a constant value to the contents of register?

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Q. Among the logic families RTL, TTL, ECL and CMOS, the fastest family is:

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Q. In the indirect addressing scheme, the second part of an instruction contains:

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Q. Amdahl’s law states that the maximum speedup S achievable by a parallel computer with ‘p’ processors is given by:

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