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Welcome to the DMA MCQs Page

Dive deep into the fascinating world of DMA with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of DMA, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of DMA, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through DMA. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of DMA. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

DMA MCQs | Page 4 of 7

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Q31.
A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following
modes this SRAM is operating

a.

Read

b.

Write

c.

Stand by

d.

None of the above

Discuss
Answer: (b).Write
Q32.
Which of the following is true with respect to EEPROM?

a.

contents can be erased byte wise only

b.

contents of full memory can be erased together

c.

contents can be erased using ultra violet rays

d.

contents can not be erased

Discuss
Answer: (c).contents can be erased using ultra violet rays
Q33.
Which microprocessor pins are used to request and acknowledge a DMA transfer?

a.

reset and ready

b.

ready and wait

c.

HOLD and HLDA

d.

None o these

Discuss
Answer: (c).HOLD and HLDA
Q34.
Software command CLEAR MASK REGISTER in DMA

a.

Disables all channels

b.

Enables all channels

c.

None

d.

Clears first/last flip-flop within 8237.

Discuss
Answer: (b).Enables all channels
Q35.
The common register(s) for all the four channels of 8257 is

a.

DMA address register

b.

Terminal count register

c.

Mode set register and status register

d.

None of the mentioned

Discuss
Answer: (c).Mode set register and status register
Q36.
The IOW (active low) in its slave mode loads the contents of a data bus to

a.

8-bit mode register

b.

upper/lower byte of 16-bit DMA address register

c.

terminal count register

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q37.
To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls

a.

HLDA signal

b.

HRQ signal

c.

DACK (active low)

d.

DACK (active high)

Discuss
Answer: (c).DACK (active low)
Q38.
The number of clock cycles required for an 8257 to complete a transfer is

a.

2

b.

4

c.

8

d.

none of the mentioned

Discuss
Answer: (b).4
Q39.
The block of 8237 that decodes the various commands given to the 8237 by the CPU is

a.

timing and control block

b.

program command control block

c.

priority block

d.

none of the mentioned

Discuss
Answer: (b).program command control block
Q40.
The priority between the DMA channels requesting the services can be resolved by

a.

timing and control block

b.

program command control block

c.

priority block

d.

none of the mentioned

Discuss
Answer: (c).priority block
Page 4 of 7

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