Q. The common register(s) for all the four channels of 8257 are

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Q. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when

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Q. The IOR (active low) input line acts as output in

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Q. The IOW (active low) in its slave mode loads the contents of data bus to

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Q. The pin that disables all the DMA channels by clearing the mode registers is

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Q. The pin that requests the access of the system bus is

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Q. The pin that is used to write data to the addressed memory location, during DMA write operation is

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Q. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is

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Q. The 8257 is able to accomplish the operation of

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Q. The bus is available when the DMA controller receives the signal

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Q. To indicate the I/O device that its request for the DMA transfer has been honoured by the CPU, the DMA controller pulls

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Q. If more than one channel requests service simultaneously, the transfer will occur as

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Q. The continuous transfer may be interrupted by an external device by pulling down the signal

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Q. The number of clock cycles required for a 8257 to complete a transfer is

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Q. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to be in

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Q. The priority of the channels varies frequently in

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Q. The register of 8257 that can only be written in is

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Q. The operation that can be performed on the status register is

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Q. In DMA the data transfer is controlled by

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Q. Cycle stealing technique is used in

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