Q. The 8257 is able to accomplish the operation of

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Q. The bus is available when the DMA controller receives the signal

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Q. To indicate the I/O device that its request for the DMA transfer has been honoured by the CPU, the DMA controller pulls

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Q. If more than one channel requests service simultaneously, the transfer will occur as

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Q. The continuous transfer may be interrupted by an external device by pulling down the signal

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Q. The number of clock cycles required for a 8257 to complete a transfer is

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Q. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to be in

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Q. The priority of the channels varies frequently in

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Q. The register of 8257 that can only be written in is

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Q. The operation that can be performed on the status register is

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Q. In DMA the data transfer is controlled by

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Q. Cycle stealing technique is used in

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Q. During DMA acknowledgement cycle, CPU relinquishes

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Q. Access time is faster for _________.

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Q. DMA stands for

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Q. If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is

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Q. In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing

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Q. If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than __________ of time must pass before another row is refreshed.

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Q. In a DMA write operation the data is transferred

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Q. Which type of JMP instruction assembles if the distance is 0020 h bytes

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