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Welcome to the DMA MCQs Page

Dive deep into the fascinating world of DMA with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of DMA, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of DMA, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through DMA. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of DMA. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

DMA MCQs | Page 3 of 7

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Q21.
In DMA the data transfer is controlled by

a.

Microprocessor

b.

RAM

c.

Memory

d.

I/O devices

Discuss
Answer: (d).I/O devices
Q22.
Cycle stealing technique is used in

a.

Interrupt based data transfer

b.

Polled mode data transfer

c.

DMA based data transfer

d.

None of these

Discuss
Answer: (c).DMA based data transfer
Q23.
During DMA acknowledgement cycle, CPU relinquishes

a.

Address bus only

b.

Address bus & control bus

c.

Control bus & data bus

d.

Data bus & address bus

Discuss
Answer: (d).Data bus & address bus
Q24.
Access time is faster for _________.

a.

ROM

b.

SRAM

c.

DRAM

d.

ERAM

Discuss
Answer: (b).SRAM
Q25.
DMA stands for

a.

Direct memory access

b.

Direct memory allocation

c.

Data memory access

d.

Data memory allocation

Discuss
Answer: (a).Direct memory access
Q26.
If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is

a.

2.5 MHz

b.

5 MHz

c.

7.5 MHz

d.

10 MHz

Discuss
Answer: (a).2.5 MHz
Q27.
In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing

a.

T1

b.

T2

c.

T3

d.

T4

Discuss
Answer: (a).T1
Q28.
If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than __________ of time must pass before another row is refreshed.

a.

64 ms

b.

4 ns

c.

0.5 ns

d.

15.625 µs

Discuss
Answer: (b).4 ns
Q29.
In a DMA write operation the data is transferred

a.

from I/O to memory

b.

from memory to I/O

c.

from memory to memory

d.

from I/O to I/O

Discuss
Answer: (a).from I/O to memory
Q30.
Which type of JMP instruction assembles if the distance is 0020 h bytes

a.

near

b.

far

c.

short

d.

None of the above

Discuss
Answer: (a).near
Page 3 of 7

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