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Welcome to the DMA MCQs Page

Dive deep into the fascinating world of DMA with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of DMA, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of DMA, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through DMA. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of DMA. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

DMA MCQs | Page 6 of 7

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Q51.
The register that keeps track of all the DMA channel pending requests and status of their terminal counts is

a.

mask register

b.

request register

c.

status register

d.

count register

Discuss
Answer: (c).status register
Q52.
The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is

a.

CLEAR

b.

SET

c.

HLDA

d.

RESET

Discuss
Answer: (d).RESET
Q53.
The DMA request input pin that has the highest priority is

a.

DREQ0

b.

DREQ1

c.

DREQ2

d.

DREQ3

Discuss
Answer: (a).DREQ0
Q54.
When interface 8237 does not have any valid pending DMA request then it is said to be in

a.

active state

b.

passive state

c.

idle state

d.

none of the mentioned

Discuss
Answer: (c).idle state
Q55.
To complete a DMA transfer, a memory to memory transfer requires

a.

a read from memory cycle

b.

a write to memory cycle

c.

a read-from and write-to memory cycle

d.

none of the mentioned

Discuss
Answer: (c).a read-from and write-to memory cycle
Q56.
In demand transfer mode of 8237, the device stops data transfer when

a.

a TC (terminal count) is reached

b.

an external EOP (active low) is detected

c.

the DREQ signal goes inactive

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q57.
The mode of 8237 in which the device transfers only one byte per request is

a.

block transfer mode

b.

single transfer mode

c.

demand transfer mode

d.

cascade mode

Discuss
Answer: (b).single transfer mode
Q58.
The transfer of a block of data from one set of memory address to another takes place in

a.

block transfer mode

b.

demand transfer mode

c.

memory to memory transfer mode

d.

cascade mode

Discuss
Answer: (c).memory to memory transfer mode
Q59.
Which of the following command is used to make all the internal registers of 8237 clear?

a.

clear first/last flipflop

b.

master clear command

c.

clear mask register

d.

none of the mentioned

Discuss
Answer: (b).master clear command
Q60.
The basic principle of floppy disks involve

a.

magnetic data reading

b.

magnetic data recording

c.

magnetic data recording and reading

d.

none of the mentioned

Discuss
Answer: (c).magnetic data recording and reading
Page 6 of 7

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