Q. The number of bus controllers that are used for interfacing of memory and I/O devices is

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Q. If the 80286 need to use system bus, then the signal that is to be active is

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Q. If MBYTES input is high, then the pin serves as

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Q. Latches are used in 80286 to

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Q. The I/O port addresses, that are not used, while designing practical systems around 80286 are

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Q. Which of the following is the highest priority usage among them?

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Q. The highest priority usage than any other usage is

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Q. The lowest priority usage among the following is

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Q. As a response to the valid bus hold request, the bus is pushed into

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Q. The bus arbiter relinquishes

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Q. A valid HOLD request is ascertained only after the completion of

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Q. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of

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Q. The slave (which is selected) sends the vector on data bus after the

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Q. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

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Q. The LOCK (active low) signal is activated during

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Q. The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is

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Q. In which of these modes, the immediate operand is included in the instruction itself?

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Q. In register address mode, the operand is stored in

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Q. In which of the following addressing mode, the offset is obtained by adding displacement and contents of one of the base registers?

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Q. In which of the following addressing mode, the offset is obtained by adding displacement, with the contents of SI?

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