Q. In minimum mode, the function of 80286 is

View solution

Q. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch and data bus cycles is

View solution

Q. By adding which of the following, the minimum mode of 80286 gives the multibus interface of 80286?

View solution

Q. The number of bus controllers that are used for interfacing of memory and I/O devices is

View solution

Q. If the 80286 need to use system bus, then the signal that is to be active is

View solution

Q. If MBYTES input is high, then the pin serves as

View solution

Q. Latches are used in 80286 to

View solution

Q. The I/O port addresses, that are not used, while designing practical systems around 80286 are

View solution

Q. Which of the following is the highest priority usage among them?

View solution

Q. The highest priority usage than any other usage is

View solution

Q. The lowest priority usage among the following is

View solution

Q. As a response to the valid bus hold request, the bus is pushed into

View solution

Q. The bus arbiter relinquishes

View solution

Q. A valid HOLD request is ascertained only after the completion of

View solution

Q. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of

View solution

Q. The slave (which is selected) sends the vector on data bus after the

View solution

Q. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

View solution

Q. The LOCK (active low) signal is activated during

View solution

Q. The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is

View solution

Q. In which of these modes, the immediate operand is included in the instruction itself?

View solution