Q. What will be the output at PORT1 if the following program is executed?

MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT

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Q. Which of the following 8085 microprocessor hardware interrupt has the lowest priority?

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Q. A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?

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Q. A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?

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Q. A CPU handles interrupt by executing interrupt service subroutine.................

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Q. Which one of the following set of gates is best suited for ‘parity’ checking and ‘parity’ generation?

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Q. ................ refers to the discrepancy among a computed, observed or measured value and the true specified or theoretically correct values.

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Q. Which logic family dissipates the minimum power ?

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Q. Which of the following electronic component is not found in IC’s ?

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Q. A given memory chip has 14 address pins and 8 data pins. It has the following number of locations.

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Q. The instruction: MOV CL, [BX] [DI] + 8 represents the ............... addressing mode.

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Q. The power dissipation of a flip-flop is 3 mW. The power dissipation of a digital system with 4 flip-flops is given by

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Q. A binary ripple counter is required to count up to 16383. How many flip-flops are required ?

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Q. Which one of the following is not an addressing mode?

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Q. Computers can have instruction formats with

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Q. Which is not a typical program control instruction?

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Q. Interrupt which arises from illegal or erroneous use of an instruction or data is

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Q. Match the following:

a. TTL                 i. High component density
b. ECL               ii. Low power consumption
c. MOS               iii. Evolution of “diodetransistor- logic”
d. CMOS           iv. High speed digital circuits

Codes:
      a   b   c    d

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Q. The branch logic that provides making capabilities in the control unit is known as

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Q. Cached and interleaved memories are ways of speeding up memory access between CPU’s and slower RAM. Which memory models are best suited (i.e. improves the performance most) for which programs ?

(i) Cached memory is best suited for small loops.
(ii) Interleaved memory is best suited for small loops
(iii) Interleaved memory is best suited for large sequential code.
(iv) Cached memory is best suited for large sequential code.

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