Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of UGC CBSE NET Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within UGC CBSE NET Exam.

Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of UGC CBSE NET Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 1 of 16

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Q1.

In which addressing mode, the effective address of the operand is generated by adding a constant value to the contents of register ?

Absolute

Indirect

Immediate

Index

Discuss

Answer: (d).Index

Q2.

The efficiency (E) and speed up (sp) for Multiprocessor with p processors satisfies

E ≤ Sp and Sp ≤ p

E ≤ 1 and Sp ≤ p

E ≤ p and Sp ≤ 1

E ≤ 1 and Sp ≤ 1

Discuss

Answer: (b).E ≤ 1 and Sp ≤ p

Q3.

In an enhancement of a CPU design, the speed of a floating point unit has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the overall speed achieved if the ratio of the number of floating point operations to the number of fixed point operations is 2 : 3 and the floating point operation used to take twice the time taken by the fixed point operation in original design ?

1.62

1.55

1.85

1.285

Discuss

Answer: (a).1.62

Q4.

Suppose a processor does not have any stack pointer registers, which of the following statements is true ?

It cannot have subroutine call instruction

It cannot have nested subroutine calls

Interrupts are not possible

All subroutine calls and interrupts are possible

Discuss

Answer: (d).All subroutine calls and interrupts are possible

Q5.

Let f be the fraction of a computation (in terms of time) that is parallelizable, P the number of processors in the system, and sp the speed up achievable in comparison with sequential execution – then the sp can be calculated using the relation :

1 /(1 - f - (f/P))

P/ P - f(P + 1)

1/ (1 - f + (f/P))

P /(P + f(P - 1))

Discuss

Answer: (c).1/ (1 - f + (f/P))

Q6.

FAN IN of a component A is defined as

Number of components that can call or pass control to component A

Number of components that are called by component A

Number of components related to component A

Number of components dependent on component A

Discuss

Answer: (a).Number of components that can call or pass control to component A

Q7.

Which of the following statements are true?

I. A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.

II. A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.

III. A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.

IV. A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.

I & II

Il & III

I, II, lll

I, III & IV

Discuss

Answer: (d).I, III & IV

Q8.

Match the following:

List -I    List - II
a. Indexed          i. is not used when an
Addressing    operand is moved from memory into a register' or from a register to memory.
b. Direct              ii.Memory address is computed by adding up two registers plus an (optional) offset.
Addressing
c. Register         iii.Addressing memory by giving a register plus a content offset.
Addressing
d. Base-             iv .can only be used to access global variables whose address 18 known at compile time. Indexed
Addressing

(a) - (ii), (b)-(i),(c)-(iv), (d)-(iii)

(a)-(ii),(b)-(iv), (c)-(i), (d)-(iii)

(a)-(iii), (b)-(iv),(c)-(i),(d)-(ii)

(a)-(iii),(b)-(i),(c)-(iv), (d)-(ii)

Discuss

Answer: (c).(a)-(iii), (b)-(iv),(c)-(i),(d)-(ii)

Q9.

Which of the following is a design criteria for instruction formats ?

The size of instructions

The number of bits in the address fields

The sufficient space in the instruction format to express all the operations desired

All of these

Discuss

Answer: (d).All of these

Q10.

Synchronization is achieved by a __________timing device which generates a periodic train of ____________

clock generator, clock pulse

master generator, clock pulse

generator, clock

master clock generator, clock pulse

Discuss

Answer: (a).clock generator, clock pulse

Page 1 of 16

Welcome to the Computer Architecture MCQs Page

Computer Architecture MCQs | Page 1 of 16

Explore more Topics under UGC CBSE NET Exam

Networking

Operating System

Software Engineering

Systems Programming

Data Structures and Algorithms

DBMS

Computer Graphics

Artificial Intelligence

Web Technologies

Theory of Computation(TOC)

Discrete Structures

Computer Arithmetic

Programming in C

UNIX System

Current Trends and Technologies

Neural Networks

Fuzzy Systems

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