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Welcome to the Computer Architecture MCQs Page

Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Computer Architecture MCQs | Page 15 of 20

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Q141.
In a two-level memory hierarchy, the access time of the memory is 12 nanoseconds and the access time of the main memory is 1.5 microseconds. The hit ratio is 0.98. What is the average access time of the two-level memory system?

a.

13.5n sec

b.

42n sec

c.

7.56n sec

d.

76n sec

Discuss
Answer: (d).76n sec
Q142.
Consider the following organization of main memory and cache memory.

Main memory: 64k ×16
Cache memory: 256 × 16

Memory is word addressable and block size of 8 words. Determine the size of tag field if the direct mapping is used for transforming data from main memory to cache memory.

a.

5 bits

b.

6 bits

c.

7 bits

d.

8 bits

Discuss
Answer: (d).8 bits
Q143.
A computer system has 4k – word cache organized in a block – set-associative manner, with 4 blocks per set, 64 words per block, memory is word addressable. The number of bits in the SET and WORD fields of the main memory address format is

a.

15, 4

b.

6, 4

c.

7, 6

d.

4, 6

Discuss
Answer: (d).4, 6
Q144.
Booth's coding in 8 bits for the decimal number −57 is:

a.

0 – 100 + 1000

b.

0 – 100 + 100 – 1

c.

0 – 1 + 100 – 10 + 1

d.

00 – 10 + 100 – 1

Discuss
Answer: (b).0 – 100 + 100 – 1
Q145.
Consider the following circuit. Which one of the following is true?

a.

f is independent of X

b.

f is independent of Y

c.

f is independent of Z

d.

None of X, Y, Z is redundant

Discuss
Answer: (c).f is independent of Z
Q146.
Identify which of the following prime implicant is not valid?

a.

A'C'D

b.

A'BD

c.

A'BC

d.

BD

Discuss
Answer: (b).A'BD
Q147.
The following truth table represents the Boolean function

a.

X

b.

X+Y

c.

XΦY

d.

Y

Discuss
Answer: (a).X
Q148.
What is the minimum number of 2 – input NAND gates are required for realizing the following function?

a.

3

b.

4

c.

5

d.

6

Discuss
Answer: (c).5
Q149.
Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays δ₁=2ns and δ₂=4ns as shown in the figure. Both XOR gates and all wires have zero delays. Assume that all gate inputs, outputs, and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns?

a.

1

b.

2

c.

3

d.

4

Discuss
Answer: (d).4
Q150.
Consider the following circuit. Except the Buffers, no gate and no connecting lead is having the delay and All inputs and outputs of gates are zero initially. Consider the timining diagram X has made. How many changes does Y undergone?

a.

2

b.

3

c.

4

d.

5

Discuss
Answer: (c).4
Page 15 of 20

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