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Welcome to the Peripherals and Interfacing with 8086 MCQs Page

Dive deep into the fascinating world of Peripherals and Interfacing with 8086 with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Peripherals and Interfacing with 8086, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of Peripherals and Interfacing with 8086, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Peripherals and Interfacing with 8086 MCQs | Page 2 of 11

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Q11.
The advantage of dynamic RAM is

a.

high packing density

b.

low cost

c.

less power consumption

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q12.
Whenever a large memory is required in a microcomputer system, the memory subsystem is generally designed using

a.

Static RAM

b.

Dynamic RAM

c.

Both static and dynamic RAM

d.

ROM

Discuss
Answer: (b).Dynamic RAM
Q13.
If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires

a.

1 transistor along with capacitance

b.

2 transistors along with resistance

c.

3 transistors along with diode

d.

2 transistors along with capacitance

Discuss
Answer: (a).1 transistor along with capacitance
Q14.
To store the charge as a representation of data, the basic dynamic RAM cell uses

a.

resistor

b.

capacitor

c.

diode

d.

transistor

Discuss
Answer: (c).diode
Q15.
The process of refreshing the data in the RAM to reduce the possibility of data loss is known as

a.

data cycle

b.

regain cycle

c.

retain cycle

d.

refresh cycle

Discuss
Answer: (d).refresh cycle
Q16.
The field in which dynamic RAM is more complicated than static RAM is

a.

complexity

b.

interfacing circuit

c.

execution unit

d.

cost

Discuss
Answer: (b).interfacing circuit
Q17.
Memory refresh activity is

a.

initialised by processor

b.

initialised by external bus master

c.

initialised by refresh mechanism

d.

initialised either by processor or by external bus

Discuss
Answer: (c).initialised by refresh mechanism
Q18.
The number of memory chips that are enabled at a time for refresh activity is

a.

2

b.

4

c.

8

d.

more than 1

Discuss
Answer: (d).more than 1
Q19.
A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is

a.

constant timer

b.

data managing timer

c.

refresh timer

d.

qualitative timer

Discuss
Answer: (c).refresh timer
Q20.
If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as

a.

n*td

b.

td/n

c.

n/td

d.

tdⁿ

Discuss
Answer: (b).td/n
Page 2 of 11

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