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Welcome to the Peripherals and Interfacing with 8086 MCQs Page

Dive deep into the fascinating world of Peripherals and Interfacing with 8086 with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Peripherals and Interfacing with 8086, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of Peripherals and Interfacing with 8086, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Peripherals and Interfacing with 8086 MCQs | Page 9 of 11

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Q81.
The number of hardware interrupts that the processor 8085 consists of is

a.

1

b.

3

c.

5

d.

7

Discuss
Answer: (c).5
Q82.
The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is

a.

Interrupt Request Register

b.

In-Service Register

c.

Priority resolver

d.

Interrupt Mask Register

Discuss
Answer: (a).Interrupt Request Register
Q83.
The register that stores the bits required to mask the interrupt inputs is

a.

In-service register

b.

Priority resolver

c.

Interrupt Mask register

d.

none of the above

Discuss
Answer: (c).Interrupt Mask register
Q84.
The interrupt control logic

a.

manages interrupts

b.

manages interrupt acknowledge signals

c.

accepts interrupt acknowledge signal

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q85.
In a cascaded mode, the number of vectored interrupts provided by 8259A is

a.

4

b.

8

c.

16

d.

64

Discuss
Answer: (d).64
Q86.
When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a

a.

input to designate chip is master or slave

b.

buffer enable

c.

buffer disable

d.

none of the above

Discuss
Answer: (b).buffer enable
Q87.
Once the ICW1 is loaded, then the initialization procedure involves

a.

edge sense circuit is reset

b.

IMR is cleared

c.

slave mode address is set to 7

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q88.
When non-specific EOI command is issued to 8259A it will automatically

a.

set the ISR

b.

reset the ISR

c.

set the INTR

d.

reset the INTR

Discuss
Answer: (b).reset the ISR
Q89.
In the application where all the interrupting devices are of equal priority, the mode used is

a.

Automatic rotation

b.

Automatic EOI mode

c.

Specific rotation

d.

EOI

Discuss
Answer: (a).Automatic rotation
Q90.
The registers that store the keyboard and display modes and operations programmed by CPU are

a.

I/O control and data buffers

b.

Control and timing registers

c.

Return buffers

d.

Display address registers

Discuss
Answer: (b).Control and timing registers
Page 9 of 11

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