Q. The number of memory chips that are enabled at a time for refresh activity is

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Q. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is

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Q. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as

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Q. The device that enables the microprocessor to read data from the external devices is

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Q. The example of output device is

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Q. The input and output operations are respectively similar to the operations,

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Q. The operation, IOWR (active low) performs

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Q. The latch or IC 74LS373 acts as

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Q. While performing read operation, one must take care that much current should not be

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Q. To avoid loading during read operation, the device used is

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Q. The chip 74LS245 is

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Q. In 74LS245, if DIR is 1, then the direction is from

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Q. In memory-mapped scheme, the devices are viewed as

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Q. Programmable peripheral input-output port is another name for

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Q. Port C of 8255 can function independently as

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Q. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called

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Q. The data bus buffer is controlled by

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Q. The input provided by the microprocessor to the read/write control logic is

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Q. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is

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Q. The port that is used for the generation of handshake lines in mode 1 or mode 2 is

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