Q. Memory refresh activity is

View solution

Q. The number of memory chips that are enabled at a time for refresh activity is

View solution

Q. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is

View solution

Q. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as

View solution

Q. The device that enables the microprocessor to read data from the external devices is

View solution

Q. The example of output device is

View solution

Q. The input and output operations are respectively similar to the operations,

View solution

Q. The operation, IOWR (active low) performs

View solution

Q. The latch or IC 74LS373 acts as

View solution

Q. While performing read operation, one must take care that much current should not be

View solution

Q. To avoid loading during read operation, the device used is

View solution

Q. The chip 74LS245 is

View solution

Q. In 74LS245, if DIR is 1, then the direction is from

View solution

Q. In memory-mapped scheme, the devices are viewed as

View solution

Q. Programmable peripheral input-output port is another name for

View solution

Q. Port C of 8255 can function independently as

View solution

Q. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called

View solution

Q. The data bus buffer is controlled by

View solution

Q. The input provided by the microprocessor to the read/write control logic is

View solution

Q. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is

View solution