Q. The common register(s) for all the four channels of 8257 is

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Q. The IOW (active low) in its slave mode loads the contents of a data bus to

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Q. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls

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Q. The number of clock cycles required for an 8257 to complete a transfer is

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Q. The block of 8237 that decodes the various commands given to the 8237 by the CPU is

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Q. The priority between the DMA channels requesting the services can be resolved by

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Q. The register that holds the current memory address is

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Q. The register that holds the data byte transfers to be carried out is

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Q. When the count becomes zero in the current word register then

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Q. The current address register is programmed by the CPU as

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Q. Which of these register’s contents is used for auto-initialization (internally)?

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Q. The register that maintains an original copy of the respective initial current address register and current word register is

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Q. The register that can be automatically incremented or decremented, after each DMA transfer is

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Q. Which of the following is a type of DMA transfer?

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Q. Each bit in the request register is cleared by

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Q. The register that holds the data during memory to memory data transfer is

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Q. The register that keeps track of all the DMA channel pending requests and status of their terminal counts is

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Q. The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is

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Q. The DMA request input pin that has the highest priority is

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Q. When interface 8237 does not have any valid pending DMA request then it is said to be in

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