Welcome to the Pipeline and Vector Processing MCQs Page

Dive deep into the fascinating world of Pipeline and Vector Processing with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Pipeline and Vector Processing, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Pipeline and Vector Processing, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

Check out the MCQs below to embark on an enriching journey through Pipeline and Vector Processing. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Pipeline and Vector Processing. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Pipeline and Vector Processing MCQs | Page 18 of 21

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Computer Architecture Basics

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8051 Microcontroller

Q171.

Indicating which of the four steps the instruction is in, is provided by

Instruction set

Instruction ID

Instruction decoding

Instruction status

Discuss

Answer: (d).Instruction status

Q172.

In pipelines with long-running operations, the possible caused issue is called

In-rage completion

Out-of-range completion

Out-of-order completion

In-order completion

Discuss

Answer: (c).Out-of-order completion

Q173.

The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is

Pipeline speedup=Pipeline depth/1 + Branch frequency

Pipeline speedup=Pipeline depth/1 - Branch frequency

Pipeline speedup=Pipeline depth*(1 + Branch frequency

Pipeline speedup=Pipeline depth/2 + Branch frequency

Discuss

Answer: (a).Pipeline speedup=Pipeline depth/1 + Branch frequency

Q174.

For execution, branch instructions require 2 cycles, store instructions require 4 cycles, and all other instructions require

2 cycles

3 cycles

4 cycles

5 cycles

Discuss

Answer: (d).5 cycles

Q175.

If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to

Time per instruction on unpipelined machine/ no of piped stages

Time per instruction on unpipelined machine* no of piped stages

Time per instruction on unpipelined machine + no of piped stages

Time per instruction on unpipelined machine - no of piped stages

Discuss

Answer: (a).Time per instruction on unpipelined machine/ no of piped stages

Q176.

If the buffer is a queue with multiple instructions, it stalls when the queue

Fills

Gets empty

Is half

None of above

Discuss

Answer: (a).Fills

Q177.

Instruction used in sequences to implement a more complex instruction set, is called a

Resuming

Nullifying

Macroinstruction

Microinstruction

Discuss

Answer: (d).Microinstruction

Q178.

A processor with separate decode and register fetch stages will probably have a

Canceling

Nullifying

Branch delay

Branch table

Discuss

Answer: (c).Branch delay

Q179.

If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a

Data hazard

Structural hazard

Pipeline hazard

Stall

Discuss

Answer: (b).Structural hazard

Q180.

Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is

4.4 ns

4.2 ns

3.4 ns

3.2 ns

Discuss

Answer: (a).4.4 ns

Page 18 of 21

Welcome to the Pipeline and Vector Processing MCQs Page

Pipeline and Vector Processing MCQs | Page 18 of 21

Explore more Topics under Computer Architecture

Computer Architecture Basics

Digital Logic Circuits

Digital Components

Digital Data Representation

Microoperations

Basic Computer Organization

Computer Arithmetic

Input Output Organization

Memory Organization

Multiprocessors

8085 Microprocessor

Microcontroller

8051 Microcontroller

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