Q. In pipelines with long-running operations, the possible caused issue is called

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Q. The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is

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Q. For execution, branch instructions require 2 cycles, store instructions require 4 cycles, and all other instructions require

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Q. If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to

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Q. If the buffer is a queue with multiple instructions, it stalls when the queue

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Q. Instruction used in sequences to implement a more complex instruction set, is called a

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Q. A processor with separate decode and register fetch stages will probably have a

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Q. If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a

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Q. Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is

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Q. The instruction in different stages of the pipeline do not interfere with one another, the separation is done by

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Q. MIPS pipeline with the appropriate registers, called pipeline registers or also known as

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Q. Pipeline interlock introduces a stall or bubble, just as in the

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Q. The time required between moving an instruction one step down the pipeline is a

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Q. A floating-point divider, a floating-point multiplier, and a floating-point adder, are the parts of a

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Q. The execution cycle with a branch, delay of one is

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Q. The hazards in the pipelined stages are of

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Q. Register $2 written by subtraction can be written in the instruction

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Q. The term specifying both the programs and the relative frequencies is known as

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Q. When multiple-instructions are overlapped during execution of the program, then function performed is called

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Q. An instruction that does no operation for changing state is known as

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