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Welcome to the Pipeline and Vector Processing MCQs Page

Dive deep into the fascinating world of Pipeline and Vector Processing with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Pipeline and Vector Processing, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Pipeline and Vector Processing, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Pipeline and Vector Processing. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Pipeline and Vector Processing. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Pipeline and Vector Processing MCQs | Page 13 of 21

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Q121.
Computing the miss penalties, for every system, the formula which can be used is

a.

Miss penalty = Memory access time*clock cycle

b.

Miss penalty = Memory access time+ clock cycle

c.

Miss penalty = Memory access time-clock cycle

d.

Miss penalty = Memory access time clock cycle

Discuss
Answer: (d).Miss penalty = Memory access time clock cycle
Q122.
The given instruction: L.D F0,0(R1), gets the state of execution in

a.

1 iteration

b.

2 iterations

c.

3 iterations

d.

4 iterations

Discuss
Answer: (b).2 iterations
Q123.
If f0 is the array element then adding the scalar in F2, can be calculated as

a.

ADDi F4,F0,F2

b.

ADD.D F4,F1,F2

c.

ADD F4,F0,F2

d.

ADD.D F4,F0,F3

Discuss
Answer: (c).ADD F4,F0,F2
Q124.
When branches are being mis-predicted; hazard which is raised due to this issue, is known as

a.

Control hazard

b.

Data hazard

c.

Stall

d.

None

Discuss
Answer: (a).Control hazard
Q125.
Considering the following code: DIV.D F0,F2,F4; ADD.D F10,F0,F8; SUB.D F12,F8,F14, one statement that is true

a.

SUB.D instruction cannot be executed

b.

Dependence of ADD.D on DIV.D

c.

Dependence of DIV.D on ADD.D

d.

both a and b

Discuss
Answer: (d).both a and b
Q126.
Branch predictors using the behavior of all other branches for making a prediction, are called

a.

Uni-relating predictors

b.

Dual-relating predictors

c.

Virtual predictors

d.

Correlating predictors

Discuss
Answer: (d).Correlating predictors
Q127.
Detection of loop stream r micro-fusion is performed by

a.

Micro-op buffer

b.

Macro-op buffer

c.

Anti-speculation

d.

Commit

Discuss
Answer: (a).Micro-op buffer
Q128.
Branch-target buffer having a single variation for storing one or more target instructions instead, or in addition to the predicted

a.

Read address

b.

Write address

c.

Target address

d.

both a and b

Discuss
Answer: (c).Target address
Q129.
Out-of-order execution of the program, tends to introduce the possibility of

a.

WAW hazards

b.

WAR hazards

c.

Data hazards

d.

both a and b

Discuss
Answer: (d).both a and b
Q130.
Three different types of dependences are

a.

Data, time, control

b.

Date, name, control

c.

Data, name, connectivity

d.

Data, name, control

Discuss
Answer: (d).Data, name, control
Page 13 of 21

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