Welcome to the Computer Architecture MCQs Page
Dive deep into the fascinating world of Computer Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Computer Architecture, a crucial aspect of UGC CBSE NET Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Computer Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within UGC CBSE NET Exam.
Check out the MCQs below to embark on an enriching journey through Computer Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of UGC CBSE NET Exam.
Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Computer Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!
Computer Architecture MCQs | Page 15 of 16
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(1-NAND gate, 2-NOR gate, 3-NOR gate)
List - I
(a) Decoder
(b) Multiplexer
(c) De multiplexer
List - II
(i) 1 line to 2^n lines
(ii) n lines to 2^n lines
(iii) 2^n lines to 1 line
(iv) 2^n lines to 2^(n−1) lines
Code:
(a) (b) (c)
(−14)10 + (−15)10
The solution in 8 bit representation is:
List - I
(a) Interrupts which can be delayed when a much highest priority interrupt has occurred
(b) Unplanned interrupts which occur while executing a program
(c) Source of interrupt is in phase with the system clock
List - II
(i) Normal
(ii) Synchronous
(iii) Maskable
(iv) Exception
Code:
(a) (b) (c)
F (A, B, C, D) = Σ (0, 1, 2, 8, 9, 12, 13)
d (A, B, C, D) = Σ (10, 11, 14, 15)
d stands for don’t care condition.
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