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Welcome to the Memory Organization MCQs Page

Dive deep into the fascinating world of Memory Organization with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Memory Organization, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Memory Organization, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Memory Organization. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Memory Organization. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Memory Organization MCQs | Page 17 of 23

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Q161.
Flash memories have limited number of the block's write cycles, these cycles must be at least

a.

1000

b.

10,000

c.

100,000

d.

100,000,00

Discuss
Answer: (c).100,000
Q162.
The Cortex-A8 known as configurable core, which supports the computer instruction set architecture of

a.

ARMv6

b.

ARMv7

c.

ARMv8

d.

ARMv9

Discuss
Answer: (b).ARMv7
Q163.
One-half of the address is first sent during the

a.

Row access strobe

b.

Column access strobe

c.

Column access cycle

d.

Row access time

Discuss
Answer: (a).Row access strobe
Q164.
Switching from one process to another. This swapping is called a

a.

Process switch

b.

Context switch

c.

Exchange

d.

both a and b

Discuss
Answer: (d).both a and b
Q165.
The very owns way for reducing capacity misses, is to increase

a.

Hit penalty

b.

Cache hit

c.

Cache capacity

d.

Fully distributive

Discuss
Answer: (c).Cache capacity
Q166.
Cache not able of containing the entire blocks needed while execution of a program, is known as

a.

Cache full

b.

Cache hit

c.

Hit rate

d.

Cache misses

Discuss
Answer: (d).Cache misses
Q167.
When cache having size 32k, block-size 64 and set the associativity 4, will have cache index of

a.

2^2

b.

2^5

c.

2^7

d.

2^9

Discuss
Answer: (c).2^7
Q168.
The cache with special address translation, is referred to as a

a.

Translation look aside bus

b.

Translation look aside buffer

c.

Transistor look aside buffer

d.

Transistor look aside bus

Discuss
Answer: (b).Translation look aside buffer
Q169.
Fetching the words in simple order, but as the requested block word arrives, send it towards the processor, is known as

a.

Early restart

b.

Restarting

c.

Start before

d.

Sequential interchange

Discuss
Answer: (a).Early restart
Q170.
The index of instruction cache is

a.

2Index= Cache size- Block size

b.

2Index= Cache size/ Block size + Set associativity

c.

2Index= Cache size+ Block size

d.

2Index= Cache size/ Block size

Discuss
Answer: (d).2Index= Cache size/ Block size
Page 17 of 23

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