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Welcome to the Basic Computer Organization MCQs Page

Dive deep into the fascinating world of Basic Computer Organization with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Basic Computer Organization, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Basic Computer Organization, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Basic Computer Organization. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Basic Computer Organization. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Basic Computer Organization MCQs | Page 4 of 13

Explore more Topics under Computer Architecture

Q31.
Which is true for a typical RISC architecture?

a.

Micro programmed control unit

b.

Instruction takes multiple clock cycles

c.

Have few registers in CPU

d.

Emphasis on optimizing instruction pipelines

Discuss
Answer: (a).Micro programmed control unit
Q32.
SIMD represents an organization that ______________.

a.

refers to a computer system capable of processing several programs at the same time.

b.

represents organization of single computer containing a control unit, processor unit and a memory unit.

c.

includes many processing units under the supervision of a common control unit.

d.

none of the above

Discuss
Answer: (c).includes many processing units under the supervision of a common control unit.
Q33.
Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus?

a.

1 Megabyte/sec

b.

4 Megabytes/sec

c.

8 Megabytes/sec

d.

2 Megabytes/sec

Discuss
Answer: (d).2 Megabytes/sec
Q34.
Von Neumann architecture is

a.

SISD

b.

SIMD

c.

MIMD

d.

MISD

Discuss
Answer: (a).SISD
Q35.
A Stack-organised Computer uses instruction of

a.

Indirect addressing

b.

Two-addressing

c.

Zero addressing

d.

Index addressing

Discuss
Answer: (c).Zero addressing
Q36.
An n-bit microprocessor has

a.

n-bit program counter

b.

n-bit address register

c.

n-bit ALU

d.

n-bit instruction register

Discuss
Answer: (d).n-bit instruction register
Q37.
PSW is saved in stack when there is a

a.

interrupt recognised

b.

execution of RST instruction

c.

execution of CALL instruction

d.

All of these

Discuss
Answer: (a).interrupt recognised
Q38.
_________ register keeps tracks of the instructions stored in program stored in memory.

a.

AR (Address Register)

b.

XR (Index Register)

c.

PC (Program Counter)

d.

AC (Accumulator)

Discuss
Answer: (c).PC (Program Counter)
Q39.
‘Aging registers’ are

a.

Counters which indicate how long ago their associated pages have been referenced.

b.

Registers which keep track of when the program was last accessed.

c.

Counters to keep track of last accessed instruction.

d.

Counters to keep track of the latest data structures referred.

Discuss
Answer: (a).Counters which indicate how long ago their associated pages have been referenced.
Q40.
Translation from symbolic program into Binary is done in

a.

Two passes

b.

Directly

c.

Three passes

d.

Four passes

Discuss
Answer: (a).Two passes
Page 4 of 13

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