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Welcome to the Operating System MCQs Page

Dive deep into the fascinating world of Operating System with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Operating System, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Operating System, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Operating System. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Operating System. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Operating System MCQs | Page 6 of 16

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Q51.
In which one of the following page replacement algorithms it is possible for the page fault rate to increase even when the number of allocated frames increases?

a.

LRU (Least Recently Used)

b.

OPT (Optimal Page Replacement)

c.

MRU (Most Recently Used)

d.

FIFO (First In First Out)

Discuss
Answer: (d).FIFO (First In First Out)
Q52.
The address sequence generated by tracing a particular program executing in a pure demand paging system with 100 bytes per page is
0100, 0200, 0430, 0499, 0510, 0530, 0560, 0120, 0220, 0240, 0260, 0320, 0410.
Suppose that the memory can store only one page and if x is the address which causes a page fault then the bytes from addresses x to x + 99 are loaded on to the memory.
How many page faults will occur ?

a.

0

b.

4

c.

7

d.

8

Discuss
Answer: (c).7
Q53.
A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-access takes 10 ns and a main memory access takes 50 ns. What is the effective access time(in ns) if the TLB hit ratio is 90% and there is no page-fault?

a.

54

b.

60

c.

65

d.

75

Discuss
Answer: (c).65
Q54.
Assume that a main memory with only 4 pages, each of 16 bytes, is initially empty. The CPU generates the following sequence of virtual addresses and uses the Least Recently Used (LRU) page replacement policy.
0, 4, 8, 20, 24, 36, 44, 12, 68, 72, 80, 84, 28, 32, 88, 92
How many page faults does this sequence cause? What are the page numbers of the pages present in the main memory at the end of the sequence?

a.

6 and 1, 2, 3, 4

b.

7 and 1, 2, 4, 5

c.

8 and 1, 2, 4, 5

d.

9 and 1, 2, 3, 5

Discuss
Answer: (b).7 and 1, 2, 4, 5
Q55.
Consider a computer with a 4-ways set-associative mapped cache of the following characteristics: a total of 1 MB of main memory, a word size of 1 byte, a block size of 128 words and a cache size of 8 KB. The number of bits in the TAG, SET and WORD fields, respectively are:

a.

7, 6, 7

b.

8, 5, 7

c.

8, 6, 6

d.

9, 4, 7

Discuss
Answer: (d).9, 4, 7
Q56.
Consider a computer with a 4-ways set-associative mapped cache of the following characteristics: a total of 1 MB of main memory, a word size of 1 byte, a block size of 128 words and a cache size of 8 KB. While accessing the memory location 0C795H by the CPU, the contents of the TAG field of the corresponding cache line is

a.

000011000

b.

110001111

c.

00011000

d.

110010101

Discuss
Answer: (a).000011000
Q57.
Which of the following is major part of time taken when accessing data on the disk?

a.

Settle time

b.

Rotational latency

c.

Seek time

d.

Waiting time

Discuss
Answer: (c).Seek time
Q58.
We describe a protocol of input device communication below. a. Each device has a distinct address b. The bus controller scans each device in sequence of increasing address value to determine if the entity wishes to communicate. c. The device ready to communicate leaves it data in IO register. d. The data is picked up and the controller moves to step-a above. Identify the form of communication best describes the IO mode among the following:

a.

Programmed mode of data transfer

b.

DMA

c.

Interrupt mode

d.

Polling

Discuss
Answer: (d).Polling
Q59.
Among the following given scenarios determine the right one to justify interrupt mode of data-transfer.

a.

Bulk transfer of several kilo-byte

b.

Moderately large data transfer but more that 1 KB

c.

Short events like mouse action

d.

None of the above

Discuss
Answer: (c).Short events like mouse action
Q60.
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?

a.

I/O protection is ensured by operating system routine(s)

b.

I/O protection is ensured by a hardware trap

c.

I/O protection is ensured during system configuration

d.

I/O protection is not possible

Discuss
Answer: (a).I/O protection is ensured by operating system routine(s)
Page 6 of 16

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