Welcome to the Operating System MCQs Page

Dive deep into the fascinating world of Operating System with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Operating System, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Operating System, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

Check out the MCQs below to embark on an enriching journey through Operating System. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Operating System. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Operating System MCQs | Page 3 of 16

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Q21.

A computer has twenty physical page frames which contain pages numbered 101 through 120. Now a program accesses the pages numbered 1, 2, …, 100 in that order, and repeats the access sequence THRICE. Which one of the following page replacement policies experiences the same number of page faults as the optimal page replacement policy for this program?

Least-recently-used

First-in-first-out

Last-in-first-out

Most-recently-used

Discuss

Answer: (d).Most-recently-used

Q22.

A system uses 3 page frames for storing process pages in main memory. It uses the Least Recently Used (LRU) page replacement policy. Assume that all the page frames are initially empty. What is the total number of page faults that will occur while processing the page reference string given below? 4, 7, 6, 1, 7, 6, 1, 2, 7, 2

Discuss

Answer: (c).6

Q23.

Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, the effective memory access time (in milliseconds) is _________.

120

122

124

118

Discuss

Answer: (b).122

Q24.

The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is __________.

1.26

1.68

2.46

4.52

Discuss

Answer: (b).1.68

Q25.

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

645 nanoseconds

1050 nanoseconds

1215 nanoseconds

1230 nanoseconds

Discuss

Answer: (d).1230 nanoseconds

Q26.

In a system with 32 bit virtual addresses and 1 KB page size, use of one-level page tables for virtual to physical address translation is not practical because of

the large amount of internal fragmentation

the large amount of external fragmentation

the large memory overhead in maintaining page tables

the large computation overhead in the translation process

Discuss

Answer: (c).the large memory overhead in maintaining page tables

Q27.

Which of the following is NOT an advantage of using shared, dynamically linked libraries as opposed to using statically linked libraries ?

Smaller sizes of executable files

Lesser overall page fault rate in the system

Faster program startup

Existing programs need not be re-linked to take advantage of newer versions of libraries

Discuss

Answer: (c).Faster program startup

Q28.

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

1.5 ns

2 ns

3 ns

4 ns

Discuss

Answer: (d).4 ns

Q29.

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 0×00400000, and a stack page starting at virtual address 0×FFFFF000. The amount of memory required for storing the page tables of this process is:

8 KB

12 KB

16 KB

20 KB

Discuss

Answer: (c).16 KB

Q30.

Which of the following is not a form of memory?

instruction cache

instruction register

instruction opcode

translation lookaside buffer

Discuss

Answer: (c).instruction opcode

Page 3 of 16

Welcome to the Operating System MCQs Page

Operating System MCQs | Page 3 of 16

Explore more Topics under GATE CSE Exam

Networking

Data Structures and Algorithms

Computer Architecture

DBMS

Compiler Design

Theory of Computation(TOC)

Engineering Mathematics

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