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Welcome to the Operating System MCQs Page

Dive deep into the fascinating world of Operating System with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Operating System, a crucial aspect of GATE CSE Exam. In this section, you will encounter a diverse range of MCQs that cover various aspects of Operating System, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within GATE CSE Exam.

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Check out the MCQs below to embark on an enriching journey through Operating System. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of GATE CSE Exam.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Operating System. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Operating System MCQs | Page 1 of 16

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Q1.
In the index allocation scheme of blocks to a file, the maximum possible size of the file depends on :

a.

the size of the blocks, and the size of the address of the blocks

b.

the number of blocks used for the index, and the size of the blocks

c.

the size of the blocks, the number of blocks used for the index, and the size of the address of the blocks

d.

None of these

Discuss
Answer: (b).the number of blocks used for the index, and the size of the blocks
Q2.
Which of the following page replacement algorithms suffers from Belady’s anomaly?

a.

FIFO

b.

LRU

c.

Optimal Page Replacement

d.

Both LRU and FIFO

Discuss
Answer: (a).FIFO
Q3.
What is the swap space in the disk used for?

a.

Saving temporary html pages

b.

Saving process data

c.

Storing the super-block

d.

Storing device drivers

Discuss
Answer: (b).Saving process data
Q4.
Increasing the RAM of a computer typically improves performance because:

a.

Virtual memory increases

b.

Larger RAMs are faster

c.

Fewer page faults occur

d.

Fewer segmentation faults occur

Discuss
Answer: (c).Fewer page faults occur
Q5.
A computer system supports 32-bit virtual addresses as well as 32-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. Which one of the following is true?

a.

Efficient implementation of multi-user support is no longer possible

b.

The processor cache organization can be made more efficient now

c.

Hardware support for memory management is no longer needed

d.

CPU scheduling can be made more efficient now

Discuss
Answer: (c).Hardware support for memory management is no longer needed
Q6.
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:

a.

11 bits

b.

13 bits

c.

15 bits

d.

20 bits

Discuss
Answer: (c).15 bits
Q7.
Virtual memory is

a.

Large secondary memory

b.

Large main memory

c.

illusion of large main memory

d.

None of the above

Discuss
Answer: (c).illusion of large main memory
Q8.
Page fault occurs when

a.

When a requested page is in memory

b.

When a requested page is not in memory

c.

When a page is currupted

d.

When an exception is thrown

Discuss
Answer: (b).When a requested page is not in memory
Q9.
Thrashing occurs when

a.

When a page fault occurs

b.

Processes on system frequently access pages not memory

c.

Processes on system are in running state

d.

Processes on system are in waiting state

Discuss
Answer: (b).Processes on system frequently access pages not memory
Q10.
A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?

a.

2

b.

4

c.

8

d.

16

Discuss
Answer: (c).8
Page 1 of 16

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