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Welcome to the Microprocessor Architecture MCQs Page

Dive deep into the fascinating world of Microprocessor Architecture with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Microprocessor Architecture, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of Microprocessor Architecture, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through Microprocessor Architecture. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Microprocessor Architecture. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Microprocessor Architecture MCQs | Page 2 of 18

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Q11.
The first machine cycle of an instruction is always

a.

A memory read cycle

b.

A fetch cycle

c.

An I/O read cycle

d.

A memory write cycle

Discuss
Answer: (b).A fetch cycle
Q12.
The output data lines of microprocessor and memories are usually tristated because

a.

More than one device can transmit information over the data bus by enabling only one device at a time

b.

More than one device can transmit over the data bus at the same time

c.

The data line can be multiplexed for both input and output

d.

It increases the speed of data transfer over the data bus

Discuss
Answer: (a).More than one device can transmit information over the data bus by enabling only one device at a time
Q13.
The correct sequence of steps in the instruction cycle of a basic computer is

a.

Fetch, Execute, Decode and Read effective address.

b.

Read effective address,Decode,Fetch and Execute.

c.

Fetch, Decode, Read effective address and ,Execute.

d.

Fetch, Read effective address, Decode and Execute.

Discuss
Answer: (c).Fetch, Decode, Read effective address and ,Execute.
Q14.
The register which holds the information about the nature of results of arithmetic and logic operations is called as

a.

Accumulator

b.

Condition code register

c.

Flag register

d.

Process status register

Discuss
Answer: (c).Flag register
Q15.
Consider the following statements:
Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?

a.

1, 2, 3 and 4

b.

1, 2 and 3

c.

1 and 2 only

d.

3 and 4 only

Discuss
Answer: (c).1 and 2 only
Q16.
Ready pin of microprocessor is used

a.

to indicate that microprocessor is ready to receive inputs

b.

to indicate that microprocessor is ready to receive outputs

c.

to introduce wait state

d.

to provide direct memory access

Discuss
Answer: (c).to introduce wait state
Q17.
Both the ALU and control section of CPU employ which special purpose storage location?

a.

Buffers

b.

Decoders

c.

Accumulators

d.

Registers

Discuss
Answer: (c).Accumulators
Q18.
A high on RESET OUT signifies that

a.

all the registers of the CPU are being reset

b.

all the registers and counters are being reset

c.

all the registers and counters are being reset and this signal can be used to reset external support chip

d.

processing can begin when this signal goes high

Discuss
Answer: (c).all the registers and counters are being reset and this signal can be used to reset external support chip
Q19.
In a vector interrupt

a.

the branch address is assigned to a fixed location in memory

b.

the interrupting source supplies the branch information to the processor through an interrupt vector

c.

the branch address is obtained from a register in the processor

d.

none of the above

Discuss
Answer: (a).the branch address is assigned to a fixed location in memory
Q20.
The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are

a.

same as the content of A7-A0

b.

irrelevant

c.

all bits reset (i.e. 00H)

d.

all bits set (i.e. FFH)

Discuss
Answer: (a).same as the content of A7-A0
Page 2 of 18

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