Question
a.
the branch address is assigned to a fixed location in memory
b.
the interrupting source supplies the branch information to the processor through an interrupt vector
c.
the branch address is obtained from a register in the processor
d.
none of the above
Posted under Microprocessor
Engage with the Community - Add Your Comment
Confused About the Answer? Ask for Details Here.
Know the Explanation? Add it Here.
Q. In a vector interrupt
Similar Questions
Discover Related MCQs
Q. The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are
View solution
Q. Which one of the following interrupt is only level triggering?
View solution
Q. Which one of the following instruction may be used to clear the accumulator content irrespective of its initial value?
View solution
Q. ___________ signal prevent the microprocessor from reading the same data more than one.
View solution
Q. Data transfer between the microprocessor for peripheral takes place through __________.
View solution
Q. 8255A operates with ________ power supply.
View solution
Q. The _______ allow data transfer between memory and peripherals.
View solution
Q. Expansion of SPGA is _________.
View solution
Q. Pentium-pro processor design implements________ micro architecture.
View solution
Q. The number of hardware chips needed for multiple digit display can be minimized by using the technique called ______.
View solution
Q. An RS-232 interface is ____________.
View solution
Q. Expansion for DTE is ______.
View solution
Q. Compared with RS-232, USB is faster and uses___________.
View solution
Q. Expansion for HMOS technology is _______.
View solution
Q. RIM is used to check whether, the ___________.
View solution
Q. What does microprocessor speed depends on?
View solution
Q. The advantage of memory mapped I/O over I/O mapped I/O is _________
View solution
Q. In 8279 Status Word, data is read when ________ pins are low, and write to the display RAM with ____________ are low.
View solution
Q. In 8279, the keyboard entries are de bounced and stored in an _________, that is further accessed by the CPU to read the key codes.
View solution
Q. For the most Static RAM the write pulse width should be at least
View solution
Suggested Topics
Are you eager to expand your knowledge beyond Microprocessor? We've curated a selection of related categories that you might find intriguing.
Click on the categories below to discover a wealth of MCQs and enrich your understanding of Computer Science. Happy exploring!
