Q. If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than __________ of time must pass before another row is refreshed.

View solution

Q. In a DMA write operation the data is transferred

View solution

Q. Which type of JMP instruction assembles if the distance is 0020 h bytes

View solution

Q. A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following
modes this SRAM is operating

View solution

Q. Which of the following is true with respect to EEPROM?

View solution

Q. Which microprocessor pins are used to request and acknowledge a DMA transfer?

View solution

Q. Software command CLEAR MASK REGISTER in DMA

View solution

Q. The common register(s) for all the four channels of 8257 is

View solution

Q. The IOW (active low) in its slave mode loads the contents of a data bus to

View solution

Q. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls

View solution

Q. The number of clock cycles required for an 8257 to complete a transfer is

View solution

Q. The block of 8237 that decodes the various commands given to the 8237 by the CPU is

View solution

Q. The priority between the DMA channels requesting the services can be resolved by

View solution

Q. The register that holds the current memory address is

View solution

Q. The register that holds the data byte transfers to be carried out is

View solution

Q. When the count becomes zero in the current word register then

View solution

Q. The current address register is programmed by the CPU as

View solution

Q. Which of these register’s contents is used for auto-initialization (internally)?

View solution

Q. The register that maintains an original copy of the respective initial current address register and current word register is

View solution

Q. The register that can be automatically incremented or decremented, after each DMA transfer is

View solution