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Welcome to the 80286 80287 Microprocessor MCQs Page

Dive deep into the fascinating world of 80286 80287 Microprocessor with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of 80286 80287 Microprocessor, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of 80286 80287 Microprocessor, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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80286 80287 Microprocessor MCQs | Page 5 of 19

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Q41.
The 80286 is available in the package as

a.

68-pin PLCC (plastic leaded chip carrier)

b.

68-pin LCC (lead less chip carrier)

c.

68-pin PGA (pin grid array)

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q42.
The clock frequency applied at the CLK pin is internally divided by

a.

2

b.

4

c.

8

d.

1

Discuss
Answer: (a).2
Q43.
The 8 address lines, A23-A16 of 80286 are zero during

a.

memory transfer

b.

address transfer

c.

memory to processor transfer

d.

I/O transfer

Discuss
Answer: (d).I/O transfer
Q44.
The signals S1 (active low), S2 (active low) are

a.

output signals

b.

indicate initiation of bus cycle

c.

define type of bus cycle with M/IO (active low)

d.

all of the mentioned

Discuss
Answer: (d).all of the mentioned
Q45.
If M/IO (active low) signal is ‘0’ then it indicates

a.

I/O cycle

b.

Memory cycle

c.

I/O cycle or INTA cycle

d.

I/O cycle or HALT cycle

Discuss
Answer: (c).I/O cycle or INTA cycle
Q46.
The LOCK (active low) is activated automatically by hardware using

a.

XCHG signal

b.

Interrupt acknowledge

c.

Descriptor table access

d.

All of the mentioned

Discuss
Answer: (d).All of the mentioned
Q47.
The pin that is used to insert wait states in a bus cycle is

a.

WAIT

b.

BHE (active low)

c.

READY (active low)

d.

WAIT(active low)

Discuss
Answer: (c).READY (active low)
Q48.
The minimum number of clock cycles required in an input pulse width of the RESET pin is

a.

4

b.

2

c.

8

d.

16

Discuss
Answer: (d).16
Q49.
To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins

a.

CAP and ground

b.

Output pin and ground

c.

CAP and Vcc

d.

NMI and ground

Discuss
Answer: (a).CAP and ground
Q50.
The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions are

a.

BUSY (active low)

b.

PEACK (active low)

c.

PEREQ

d.

ERROR (active low)

Discuss
Answer: (d).ERROR (active low)
Page 5 of 19

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